Design Goals

Design Description

A power-supply margining circuit is used for tuning the output of a power converter. This is done either to adjust the offset and drift of the power supply output or to program a desired value at the output. Adjustable power supplies like Low-Dropout Regulators (LDOs) and DC/DC converters provide a feedback or adjust input that is used to set the desired output. A precision voltage output digital-to-analog converter (DAC) is designed for controlling the power-supply output linearly. The following image shows an example power-supply margining circuit. Typical applications of power-supply margining is in test and measurement, communications equipment, and power delivery.

Design Notes

1. Choose a DAC with the required resolution, pulldown resistor value, and output range.
2. Derive the relationship of the DAC output to V_OUT.
3. Choose R₁ based on typical current through the feedback circuit.
4. Calculate the start-up or nominal value of V_DAC considering the power-down and power-up conditions of the DAC.
5. Select R₂, and R₃ such that the desired start-up output voltage is met along with the DAC output voltage range for the desired tuning range.
6. Calculate the margin low and margin high DAC outputs.
7. Choose a compensation capacitor to achieve the desired step response.

Design Steps

1. Select the LDO TPS79501 device for the calculations. The DAC53608 device is an ultra-low cost, 10-bit, 8-channel, unipolar output DAC designed for such applications
2. The output voltage of the power supply is given by:
   

   where

   • I₁ is the current flowing through R₁
   • I₂ is the current flowing through R₂
   • I₃ is the current flowing through R₃

   DACs in this application typically include power-down mode, which includes an internal pulldown resistor at the voltage output. Hence, replacing the values of the currents in the previous equation yields:

   • When the DAC is in Power Down mode:
     
   • When the DAC output is powered-up:
     

   For DAC53608, R_PULL-DOWN is 10kΩ. For the LDO part number TPS79501, the value of V_REF is 1.225V.

3. R₁ can be calculated by the following method.
   The current through the FB pin of TPS79501 is 1µA. To make this current negligible, I₁ should be >> I_FB. Choose I₁ to be 50µA. Calculate R₁ as follows:
   

   The nominal value of I₁ can be given by:

   • When the DAC is in Power Down mode
     
   • When the DAC output is powered-up
     

   The values of I₁ at Margin High and Margin Low outputs are given by:

   
   
   
4. The nominal or startup value of V_DAC can be calculated using the following method:

   To make sure the 10-kΩ resistor does not impact when the DAC is transitioning from power-down to power-up, the power-up value for the DAC voltage can be calculated with:

   

   The previous equation can be further simplified to:

   
5. The values of R₂ and R₃ can be calculated as follows:

   If the power-up or nominal value of V_DAC is kept at one-third of V_REF, that is, 408.3mV, then R₃ is 2 × 10kΩ = 20kΩ. R₂ can be calculated as:

   

   Replacing the value of R₃, R₂ can be calculated to equal 133kΩ.

6. Subtracting the Margin High and Nominal values of I₁ and the corresponding equations, we get
   

   So, the Margin High value of V_DAC is 249mV and similarly, the Margin Low value can be calculated as 567mV from the following equation:

   
7. The step response of this circuit without a compensation capacitor has some overshoot and ringing as shown in the following curves. This kind of transient response can cause errors at the load circuits. To minimize this, use a compensation capacitor C₁. The value of this capacitance is usually obtained through simulation. A comparative output shows the waveforms with a compensation capacitor of 22pF.

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