TI provides SDFM module development sample code in F2837 family in the ControSUITE software development package. Please refer to the ControlSUITE installation path:

C:\ti\controlSUITE\device_support\F2837xD\v210\F2837xD_examples_Cpu1\sdfm_pwm_sync_cpu\cpu01sdfm_pwm_sync_cpu_cpu01.c

The default sample code does not work and requires EPWM module configuration and SDFM module configuration before minimal system of AMC1305M25 and F28377S can work.

The configuration steps are shown as follows:

1. F28377S can use EPWM module to generate the clock signal required by AMC1305M25. In this example, the clock configuration is shown in Figure 3-2. In this way, EPWMCLK in EPWM3A (GPIO4) module, is divided down to 100MHz, and the counting mode UP_DOWN is used. The final GPIO4 output clock is 10MHz.

   Figure 3-2 Using GPIO4 - Configuring clock frequency to 10MHz
2. Configure SIGMA-DELTA filter

   The sdfm_configureData_filter() function is available in F28377S library to directly configure SDFM filter type, oversampling ratio and output data bit length. In the next input short-circuit noise test, the main modified filter type is SINC1, SINC2 and SINC3; the oversampling ratio is OSR=64, OSR=128 and OSR=256.

   

The software configuration is complete and the minimal system functionality of AMC1305M25 and F28377S needs to be verified. Short the input terminal J2 of AMC1305M25 evaluation module to power GND as shown in Figure 3-3.

Observe CLK_IN and DOUT pins with an oscilloscope probe. At this point, CLK_IN data clock frequency should be 10MHz. DOUT outputs digital signals “1” and “0” since the input differential signal is 0V, as shown in Figure 3-4. DOUT output may encounter a situation where two consecutive clock data are both “1”. In this case, the data for the next two clock cycles will be “0”, and the output clock will maintain a 50% duty cycle state. This waveform indicates that the minimal system hardware is properly connected and that AMC1305M25 is correctly getting 0V input data.