Introduction

1. A large current draw from the 48V rail
2. A voltage increase on the 12V rail
3. Energy surge in the reverse direction across the 12V/5V Load Driver

Figure 1 48V -> 12V Short Overview Diagram

In Zone Control Module (ZCM) applications, many devices are vulnerable to these short events. Affected devices fall into two categories: Inputs and Outputs. This paper focuses on the following output (off-board load driver) device types:

1. Smart eFuses
2. High Side Switches (HSS)
3. Motor Drivers (MD)
4. Voltage-Tracking Low Dropout Regulators (LDOs)

48V Load Driver Shutdown Behaviors

1. Immediate Shutdown: The FET turns off instantly when the short circuit current threshold is reached.
2. Current Regulation: The device regulates current and only turns off the FET upon reaching thermal shutdown (TSD).

Smart eFuses

The TPS2HCS08-Q1 was selected as the 12V smart eFuse device under test (DUT). Tests were conducted using both a 48V HSS (TPS1HTC30-Q1) and a 48V MD (DRV8163-Q1) as the 48V load driver, since their differing behavioral responses impact the survival of downstream 12V devices.

Figure 2 shows the first test setup, which uses the TPS1HTC30-Q1 for the 48V HSS and the TPS2HCS08-Q1 smart eFuse.

Figure 2 Test Setup with TPS2HCS08-Q1 and TPS1HTC30-Q1

See Test Procedure and Setup Parameters for the procedure followed.

Figure 3 and Figure 4 show test results.

Figure 3 TPS2HCS08-Q1 FET On Short to TPS1HTC30-Q1

Figure 4 TPS2HCS08-Q1 FET Off Short to TPS1HTC30-Q1

Figure 3 and Figure 4 show the results of shorting the 12V eFuse output to the 48V HSS output, with the 12V eFuse FET initially ON (Figure 3) and initially OFF (Figure 4). Both results show a voltage rise on the input and output of the 12V eFuse channel, with the 48V input rail remaining stable. The short circuit current is consistent with the expected behavior documented in the TPS1HTC30-Q1 datasheet. No failures were observed across repeated tests.

Figure 5 shows the second test setup, which uses the DRV8163-Q1 for the 48V HSS and the TPS2HCS08-Q1 smart eFuse.

Figure 5 Test Setup with TPS2HCS08-Q1 and DRV8163-Q1

See Test Procedure and Setup Parameters for the procedure followed.

Figure 6 and Figure 7 show test results.

Figure 6 TPS2HCS08-Q1 FET On Short to DRV8163-Q1

Figure 7 TPS2HCS08-Q1 FET Off Short to DRV8163-Q1

Figure 6 and Figure 7 show the results of shorting the 12V eFuse output to the 48V MD output — with the 12V eFuse FET initially ON (Figure 6) and initially OFF (Figure 7). Both results show a voltage rise on the input and output of the 12V eFuse channel, with the 48V battery rail remaining relatively stable. The short circuit current is consistent with the expected behavior of the DRV8163-Q1 at the configured short circuit threshold. No failures were observed across repeated tests.

Smart eFuse Test Summary:

No device damage was observed in any of the above tests. Based on these results, no additional protection circuitry is required for the 12V smart eFuse.

To conclude, wire inductance may affect motor drivers (or ICs with an immediate short circuit shutdown) more than HSS. Since V = Ldi/dt, and assuming V is constant, if L increases, then di/dt decreases. Thus, cable inductance can widen the area under the short circuit curve for these devices, which can affect the energy across the TPS2HCS08. Wire inductance seems to be less crucial for the HSS since these devices shutdown once they reach TSD (thermal shutdown). The energy across these HSS devices may differ, but so will the amount of time the devices see this energy. Ultimately the concern for the HSS is not inductance but more so the amount of capacitance, which determines how much energy is dumped across this device, which determines how long the device survives for.

High Side Switch (HSS)

The TPS4HC120-Q1 was selected as the 12V DUT. See Test Procedure and Setup Parameters for the procedure followed.

Figure 8 shows the first test setup, which uses the TPS1HTC30-Q1 for the 48V HSS and the TPS4HC120-Q1 HSS.

Figure 8 Test Setup with TPS4HC120-Q1 and TPS1HTC30-Q1

Figure 9 and Figure 10 shows test results.

Figure 9 TPS4HC120-Q1 FET On Short to TPS1HTC30-Q1 (8A CL)

Figure 10 TPS4HC120-Q1 FET On Short to TPS1HTC30-Q1 (16A CL)

Figure 11 shows the second test setup, which uses the DRV8163-Q1 for the 48V HSS and the TPS4HC120-Q1 HSS.

Figure 11 Test Setup with TPS4HC120-Q1 and DRV8163-Q1

Figure 12 shows test results.

Figure 12 TPS4HC120-Q1 FET Short to DRV8163-Q1

HSS Test Summary

When shorting to the DRV8163-Q1, the short circuit protection (SCP) shuts off the output, protecting the downstream TPS4HC120-Q1. When shorting to the TPS1HTC30-Q1, the current limiting response does not make sure that current flow will be interrupted before damage occurs to the TPS4HC120-Q1.

Proposed Protection: Place a series input blocking diode on the HSS input to prevent reverse current from damaging the device.

Motor Drivers (MD)

The DRV8245-Q1 was selected as the 12V DUT. See Test Procedure and Setup Parameters for the procedure followed.

Figure 13 shows details the first test setup, which uses the TPS1HTC30-Q1 for the 48V HSS and the DRV8245-Q1 MD.

Figure 13 Test Setup with DRV8245-Q1 and TPS1HTC30-Q1

Figure 14 and Figure 15 show test results.

Figure 14 DRV8245-Q1 FET Short to TPS1HTC30-Q1 (8A CL)

Figure 15 DRV8245-Q1 FET Short to TPS1HTC30-Q1 (16A CL)

Figure 16 shows the second test setup, which uses the DRV8163-Q1 for the 48V HSS and the DRV8245-Q1 MD.

Figure 16 Test Setup with DRV8245-Q1 and DRV8163-Q1

See Test Procedure and Setup Parameters for the procedure followed.

Figure 17 shows test results.

Figure 17 DRV8245-Q1 FET On Short to DRV8163-Q1

MD Test Summary:

When shorting to the TPS1HTC30-Q1, it is not verified that the device shuts off in time to prevent reverse current flow into the DRV8245-Q1. When shorting to the DRV8163-Q1, while the DRV8163-Q1 does shut off via SCP, this does not occur before the absolute maximum voltage rating of the DRV8245-Q1 is violated.

Proposed Protection

• Series input blocking diode placed at the input of the 12V MD to prevent reverse current from damaging the device
• Output TVS diode placed on the output of the 12V MD to clamp the output voltage below the device's absolute maximum rating

Voltage-Tracking LDO

Tracking LDOs supply power off-board to loads and sensors through long wire harnesses, making them susceptible to output-side shorts to the 48V battery — even when powered from a 12V supply. The TPS7B4255-Q1 was selected as the DUT. Refer to the test procedure section for the procedure followed.

Figure 18 shows the first test setup, which uses the TPS1HTC30-Q1 for the 48V HSS and the TPS7B4255-Q1 LDO.

Figure 18 Test Setup with TPS7B4255-Q1 and TPS1HTC30-Q1

Figure 19 shows test results.

Figure 19 TPS7B4255-Q1 Short to TPS1HTC30-Q1 (8A CL)

Figure 20 shows the second test setup, which uses the DRV8163-Q1 for the 48V HSS and the TPS7B4255-Q1 LDO.

Figure 20 Test Setup with TPS7B4255-Q1 and DRV8163-Q1

Figure 21 and Figure 22 show test results.

Figure 21 TPS7B4255-Q1 Short to DRV8163-Q1 (C_OUT Additional = 0uF)

Figure 22 TPS7B4255-Q1 Short to DRV8163-Q1 (C_OUT Additional = 2.2uF)

Tracking LDO Test Summary

Without additional output capacitance: The device's internal reverse current protection (RCP) does not respond quickly enough, allowing high current to flow through the internal FET and cause damage. The TPS7B4255-Q1’s RCP response time is 0.5µs maximum for the given test conditions. Therefore, it follows that the reverse current condition occurs in <0.5µs, a timescale shorter than that which is required for an output short to a 12V automotive battery

With additional output capacitance (tested as low as 2.2 µF): The device survives. The extra capacitance provides sufficient response time for the LDO to activate RCP (within 0.5µs) before damage occurs. However, although the device survives, the V_OUT abs max is still violated. Therefore adding more C_OUT is not a sufficient protection solution.

For more information on preventing reverse current in LDOs, see LDO Basics: Preventing Reverse Current

To verify the tracking LDOs remain protected, the circuit in Figure 23 is proposed:

Figure 23 LDO Protection Circuit

The protection circuit limits the voltage on OUT to V_GATE + V_DIODE steady state during a short to the _48V battery on the output.

A fast transient from typical operation to output short can cause an initially higher voltage on OUT, as a result of leakage through the protection FET. With nominal V_OUT of the TPS7B4255-Q1 programmed as high as 35V, the voltage transient is limited within device absolute maximum ratings. If the short condition persists, the voltage on OUT eventually settles to V_GATE + V_DIODE. This is because once the LDO sees the higher voltage on OUT, it will attempt to regulate the output down, which will drive V_GATE low and turn the protection FET off. If the short on the LDO output is cleared, output recovers and the protection FET returns to the ON state.

Test Results and Protection Designs Summary

Test Procedure and Setup Parameters

Test procedure when using the TPS1HTC30-Q1 48V HSS:

1. Make sure both switches (SW1, SW2) and the relay are open.
2. Close SW1.
3. Turn on 48V supply.
4. Enable the TPS1HTC30-Q1 FET.
5. Close SW2.
6. Open SW1.
7. Drive the relay to create the short between 48V and the lower voltage rail.

Test procedure when using the DRV8163-Q1 48V MD:

1. Make sure both switches (SW1, SW2) and the relay are open.
2. Close SW1.
3. Turn on 48V supply.
4. Drive DRV8163-Q1 HS FET.
5. Close SW2.
6. Open SW1.
7. Drive the relay to create the short between 48V and the lower voltage rail.

The following test setup parameters were used for all test setups.

Conclusion