SBAS734D March   2017  – August 2026 AMC1306E05 , AMC1306E25 , AMC1306M05 , AMC1306M25

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics (AMC1306x05)
    10. 6.10 Electrical Characteristics (AMC1306x25)
    11. 6.11 Switching Characteristics
    12. 6.12 Timing Diagrams
    13. 6.13 Insulation Characteristics Curves
    14. 6.14 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 Modulator
      3. 7.3.3 Isolation Channel Signal Transmission
      4. 7.3.4 Digital Output
      5. 7.3.5 Manchester Coding Feature
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fail-Safe Output
      2. 7.4.2 Output Behavior in Case of a Full-Scale Input
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Digital Filter Usage
    2. 8.2 Typical Applications
      1. 8.2.1 Frequency Inverter Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Isolated Voltage Sensing
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
      3. 8.2.3 What To Do and What Not To Do
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
        1. 9.1.1.1 Isolation Glossary
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.9 Electrical Characteristics (AMC1306x05)

minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 3.0V to 5.5V, DVDD = 2.7V to 5.5V, AINP = –50mV to 50mV, AINN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted); typical specifications are at TA = 25°C, CLKIN = 20MHz, AVDD = 5V, and DVDD = 3.3V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
VCMov Commonmode overvoltage detection level (INP + INN) / 2 to AGND AVDD – 2 V
CIN Single-ended input capacitance INN = AGND 4 pF
CIND Differential input capacitance 2 pF
RIN Single-ended input resistance INN = AGND 4.75 kΩ
RIND Differential input resistance 4.9 kΩ
IIB Input bias current INP = INN = AGND, IIB = IBP + IBN –97 –72 –57 μA
IIO Input offset current ±10 nA
CMTI Common-mode transient immunity 50 100 kV/μs
CMRR Common-mode rejection ratio INP = INN, fIN = 0Hz, VCM min ≤ VIN ≤ VCM max –99 dB
INP = INN, fIN from 0.1Hz to 50kHz,VCM min ≤ VIN ≤ VCM max –98
BW Input bandwidth 800 kHz
DC ACCURACY
DNL Differential nonlinearity Resolution: 16 bits –0.99 0.99 LSB
INL Integral nonlinearity(3) Resolution: 16 bits,
4.5V ≤ AVDD ≤ 5.5V		 –4 ±1 4 LSB
Resolution: 16 bits,
3.0V ≤ AVDD ≤ 3.6V		 –5 ±1.5 5 LSB
EO Offset error(1) TA = 25°C, INP = INN = GND1 –50 ±2.5 50 µV
TCEO Offset error temperature drift(4) –1 ±0.25 1 μV/°C
EG Gain error TA = 25°C –0.2% ±0.005% 0.2%
TCEG Gain error temperature drift(5) –40 ±20 40 ppm/°C
PSRR Power-supply rejection ratio INP = INN = AGND,
AVDD from 3.0V to 5.5V, at DC		 –108 dB
INP = INN = AGND,
AVDD from 3.
0V to 5.5V, 10kHz / 100mV ripple		 –107
AC ACCURACY
SNR Signal-to-noise ratio fIN = 1kHz 78 82.5 dB
SINAD Signal-to-noise + distortion fIN = 1kHz 77.5 82.3 dB
THD Total harmonic distortion(6) 4.5V ≤ AVDD ≤ 5.5V, fIN = 1kHz, 5MHz ≤ fCLKIN ≤ 21MHz –98 –84 dB
3.0V ≤ AVDD ≤ 3.6V, fIN = 1kHz, 5MHz ≤ fCLKIN ≤ 20MHz –93 –83
SFDR Spurious-free dynamic range fIN = 1kHz 83 100 dB
CMOS LOGIC WITH SCHMITT-TRIGGER
IIN Input current DGND ≤ VIN ≤ DVDD 0 7 μA
CIN Input capacitance 4 pF
VIH High-level input voltage 0.7 × DVDD DVDD + 0.3 V
VIL Low-level input voltage –0.3 0.3 × DVDD V
CLOAD Output load capacitance 30 pF
VOH High-level output voltage IOH = –20µA DVDD – 0.1 V
IOH = –4mA DVDD – 0.4
VOL Low-level output voltage IOL = 20µA 0.1 V
IOL = 4mA 0.4
POWER SUPPLY
IAVDD High-side supply current 3.0V ≤ AVDD ≤ 3.6V 6.3 8.5 mA
4.5V ≤ AVDD ≤ 5.5V 7.2 9.8
IDVDD Low-side supply current AMC1306Ex, 2.7V ≤ DVDD ≤ 3.6V,
CLOAD = 15pF		 4.1 5.5 mA
AMC1306Mx, 2.7V ≤ DVDD ≤ 3.6V,
CLOAD = 15pF		 3.3 4.8
AMC1306Ex, 4.5V ≤ DVDD ≤ 5.5V,
CLOAD = 15pF		 5.0 6.9
AMC1306Mx, 4.5V ≤ DVDD ≤ 5.5V,
CLOAD = 15pF		 3.9 6.0
(1) This parameter is input referred.
(2) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.
(3) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCEO = (EO,MAX – EO,MIN) / TempRange where EO,MAX and EO,MIN refer to the maximum and minimum EO values measured within the temperature range (–40 to 125℃).
(4) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = ((EG,MAX - EG,MIN) / TempRange) x 104 where EG,MAX and EG,MIN refer to the maximum and minimum EG values (in %) measured within the temperature range (–40 to 125℃).
(5) THD is the ratio of the rms sum of the amplitudes of first five higher harmonics to the amplitude of the fundamental.