SBAS734D March   2017  – August 2026 AMC1306E05 , AMC1306E25 , AMC1306M05 , AMC1306M25

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics (AMC1306x05)
    10. 6.10 Electrical Characteristics (AMC1306x25)
    11. 6.11 Switching Characteristics
    12. 6.12 Timing Diagrams
    13. 6.13 Insulation Characteristics Curves
    14. 6.14 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 Modulator
      3. 7.3.3 Isolation Channel Signal Transmission
      4. 7.3.4 Digital Output
      5. 7.3.5 Manchester Coding Feature
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fail-Safe Output
      2. 7.4.2 Output Behavior in Case of a Full-Scale Input
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Digital Filter Usage
    2. 8.2 Typical Applications
      1. 8.2.1 Frequency Inverter Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Isolated Voltage Sensing
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
      3. 8.2.3 What To Do and What Not To Do
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
        1. 9.1.1.1 Isolation Glossary
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.11 Switching Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tH DOUT hold time after rising edge of CLKIN CLOAD = 15pF 3.5 ns
tD Rising edge of CLKIN to DOUT valid delay CLOAD = 15 pF 15 ns
tr DOUT rise time 10% to 90%, 2.7V ≤ DVDD ≤ 3.6V, CLOAD = 15pF 0.8 3.5 ns
10% to 90%, 4.5V ≤ DVDD ≤ 5.5V, CLOAD = 15pF 1.8 3.9
tf DOUT fall time 10% to 90%, 2.7V ≤ DVDD ≤ 3.6V, CLOAD = 15pF 0.8 3.5 ns
10% to 90%, 4.5V ≤ DVDD ≤ 5.5V, CLOAD = 15pF 1.8 3.9
tISTART Interface startup time DVDD at 2.7V (min) to DOUT valid with AVDD ≥ 3.0V 32 32 CLKIN
cycles
tSTART Analog start-up time AVDD step from 0 to 3.0V with DVDD ≥ 2.7V to bitstream valid, 0.1% settling 0.5 ms