SBASAL3B September   2024  â€“ June 2025 ADC3668 , ADC3669

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (ADC3668 - 250 MSPS)
    8. 6.8  Electrical Characteristics - AC Specifications (ADC3669 - 500 MSPS)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics, ADC3668
    11. 6.11 Typical Characteristics, ADC3669
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
        1. 8.3.1.1 Nyquist Zone Selection
        2. 8.3.1.2 Analog Front End Design
      2. 8.3.2 Sampling Clock Input
      3. 8.3.3 Multi-Chip Synchronization
        1. 8.3.3.1 SYSREF Monitor
      4. 8.3.4 Time-Stamp
      5. 8.3.5 Overrange
      6. 8.3.6 External Voltage Reference
      7. 8.3.7 Digital Gain
      8. 8.3.8 Decimation Filter
        1. 8.3.8.1 Uncommon Decimation Ratios
        2. 8.3.8.2 Decimation Filter Response
        3. 8.3.8.3 Decimation Filter Configuration
        4. 8.3.8.4 Numerically Controlled Oscillator (NCO)
      9. 8.3.9 Digital Interface
        1. 8.3.9.1 Parallel LVDS (DDR)
        2. 8.3.9.2 Serial LVDS (SLVDS) with Decimation
          1. 8.3.9.2.1 SLVDS - Status Bit Insertion
        3. 8.3.9.3 Output Data Format
        4. 8.3.9.4 32-bit Output Resolution
        5. 8.3.9.5 Output Scrambler
        6. 8.3.9.6 Output MUX
        7. 8.3.9.7 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Latency Mode
      2. 8.4.2 Digital Channel Averaging
      3. 8.4.3 Power Down Mode
    5. 8.5 Programming
      1. 8.5.1 GPIO Programming
      2. 8.5.2 Register Write
      3. 8.5.3 Register Read
      4. 8.5.4 Device Programming
      5. 8.5.5 Register Map
      6. 8.5.6 Detailed Register Description
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Wideband Spectrum Analyzer
      2. 9.2.2 Design Requirements
        1. 9.2.2.1 Input Signal Path
        2. 9.2.2.2 Clocking
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Sampling Clock
      4. 9.2.4 Application Performance Plots
      5. 9.2.5 Initialization Set Up
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.5.5 Register Map

Table 8-18 Register Map Summary
REGISTER
ADDRESS		 REGISTER DATA
A[11:0] D7 D6 D5 D4 D3 D2 D1 D0
0x25 0 0 0 CFG RDY 0 0 0 0
0x100 0 0 0 0 0 0 0 RESET
0x101 0 0 0 GBL PDN 0 0 0 0
0x102 0 SYSREF DET CLR 0 0 0 0 0 0
0x104 0 0 0 0 0 0 CHB TERM CHA TERM
0x10A 0 0 0 0 0 OVR CLR OVR STICKY
0x10B OVR LENGTH
0x110 LVDS TERM 0 LVDS HALF SWING 0 0 0 SWAP CH 0
0x111 LVDS DATA INV [7:0]
0x112 LVDS DATA INV [15:8]
0x113 LVDS PDN [14:8] 0
0x114 0 0 0 0 0 0 0 LVDS PDN [15]
0x115 0 0 0 0 FCLK DC FCLK DIS 0 0
0x116 LVDS MUX EN LVDS SWAP EDGE 0 0 0 LVDS SCR
0x117 DOUT1 MUX DOUT0 MUX
0x118 DOUT3 MUX DOUT2 MUX
0x119 DOUT5 MUX DOUT4 MUX
0x11A DOUT7 MUX DOUT6 MUX
0x11B DOUT9 MUX DOUT8 MUX
0x11C DOUT11 MUX DOUT10 MUX
0x11D DOUT13 MUX DOUT12 MUX
0x11E DOUT15 MUX DOUT14 MUX
0x132 HIGH FIN 0 0 0 0 0 0 0
0x140 0 SYSREF DET SYSREF OR SYSREF X5 SYSREF X4 SYSREF X3 SYSREF X2 SYSREF X1
0x146 0 0 0 GPIO CONFIG
0x14A 0

0

 0 PATTERN CLK 0 TEST PATTERN
0x14B CUSTOM PATTERN [7:0]
0x14C CUSTOM PATTERN [15:8]
0x14D 0 0 0 0 CUSTOM PATTERN [19:16]
0x15B DIGITAL GAIN CHA
0x15C DIGITAL GAIN CHB
0x160 0 0 0 0 0

0

 SYSREF MODE
0x161 LVDS SYSREF MASK DDC SYSREF MASK NCO SYSREF MASK TIMER SYSREF MASK
0x162 SYSREF TIME STAMP 0 6dB GAIN OVERRIDE COMPLEX DDC EN OUTPUT RES OUTPUT FORMAT
0x163 DDC3 MUX DDC2 MUX DDC1 MUX DDC0 MUX
0x164 NCO3 UPDATE NCO2 UPDATE NCO1 UPDATE NCO0 UPDATE SEL NEG IM 0 0 NCO MODE
0x165 0 0 0 LOW LATENCY EN 0 DIS NCO AUTO UPDATE NCO SEL EN NCO COMMON UPDATE
0x166 DDC3 NCO SEL DDC2 NCO SEL DDC1 NCO SEL DDC0 NCO SEL
0x167 DDC1 DECIMATION DDC0 DECIMATION
0x168 DDC3 DECIMATION DDC2 DECIMATION
0x169 UNEQUAL DECIMATION 0 NUM OF DDCS COMMON DECIMATION
0x16B 0 0 UPDATE NYQUIST ZONE 0 0 NYQUIST_ZONE
0x205..0x200 DDC0 NCO FREQUENCY0 [47:0]
0x20B..0x206 DDC0 NCO FREQUENCY1 [47:0]
0x211..0x20C DDC0 NCO FREQUENCY2 [47:0]
0x217..0x212 DDC0 NCO FREQUENCY3 [47:0]
0x219/0x218 DDC0 NCO PHASE0 [15:0]
0x21B/0x21A DDC0 NCO PHASE1 [15:0]
0x21D/0x21C DDC0 NCO PHASE2 [15:0]
0x21F/0x21E DDC0 NCO PHASE3 [15:0]
0x245..0x240 DDC1 NCO FREQUENCY0 [47:0]
0x24B..0x246 DDC1 NCO FREQUENCY1 [47:0]
0x251..0x24C DDC1 NCO FREQUENCY2 [47:0]
0x257..0x252 DDC1 NCO FREQUENCY3 [47:0]
0x259/0x258 DDC1 NCO PHASE0 [15:0]
0x25B/0x25A DDC1 NCO PHASE1 [15:0]
0x25D/0x25C DDC1 NCO PHASE2 [15:0]
0x25F/0x25E DDC1 NCO PHASE3 [15:0]
0x285..0x280 DDC2 NCO FREQUENCY0 [47:0]
0x28B..0x286 DDC2 NCO FREQUENCY1 [47:0]
0x291..0x28C DDC2 NCO FREQUENCY2 [47:0]
0x297..0x292 DDC2 NCO FREQUENCY3 [47:0]
0x299/0x298 DDC2 NCO PHASE0 [15:0]
0x29B/0x29A DDC2 NCO PHASE1 [15:0]
0x29D/0x29C DDC2 NCO PHASE2 [15:0]
0x29F/0x29E DDC2 NCO PHASE3 [15:0]
0x2C5...0x2C0 DDC3 NCO FREQUENCY0 [47:0]
0x2CB..0x2C6 DDC3 NCO FREQUENCY1 [47:0]
0x2D1..0x2CC DDC3 NCO FREQUENCY2 [47:0]
0x2D7..0x2D2 DDC3 NCO FREQUENCY3 [47:0]
0x2D9/0x2D8 DDC3 NCO PHASE0 [15:0]
0x2DB/0x2DA DDC3 NCO PHASE1 [15:0]
0x2DD/0x2DC DDC3 NCO PHASE1 [15:0]
0x2DF/0x2DE DDC3 NCO PHASE3 [15:0]
0x590 0 0 0 0 0 0 ENABLE DCLK DIVIDER 0
0x691 LVDS PDN [5:7] DCLK PD 0 0 0 0
0x692 0 0 0 LVDS PDN [0:4]