SBASAN5A
July 2023 – May 2025
AFE7955
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Specifications
4.1
Absolute Maximum Ratings
4.2
ESD Ratings
4.3
Recommended Operating Conditions
4.4
Thermal Information AFE79xx
4.5
Transmitter Electrical Characteristics
4.6
RF ADC Electrical Characteristics
4.7
PLL/VCO/Clock Electrical Characteristics
4.8
Digital Electrical Characteristics
4.9
Power Supply Electrical Characteristics
4.10
Timing Requirements
4.11
Switching Characteristics
4.12
Typical Characteristics
4.12.1
TX Typical Characteristics 800 MHz
4.12.2
TX Typical Characteristics at 1.8 GHz
4.12.3
TX Typical Characteristics at 2.6 GHz
4.12.4
TX Typical Characteristics at 3.5 GHz
4.12.5
TX Typical Characteristics at 4.9 GHz
4.12.6
TX Typical Characteristics at 8.1 GHz
4.12.7
TX Typical Characteristics at 9.6 GHz
4.12.8
RX Typical Characteristics at 800 MHz
4.12.9
RX Typical Characteristics at 1.75-1.9 GHz
4.12.10
RX Typical Characteristics at 2.6 GHz
4.12.11
RX Typical Characteristics at 3.5 GHz
4.12.12
RX Typical Characteristics at 4.9 GHz
4.12.13
RX Typical Characteristics at 8.1GHz
4.12.14
RX Typical Characteristics at 9.6 GHz
4.12.15
PLL and Clock Typical Characteristics
5
Device and Documentation Support
5.1
Receiving Notification of Documentation Updates
5.2
Support Resources
5.3
Trademarks
5.4
Electrostatic Discharge Caution
5.5
Glossary
6
Revision History
7
Mechanical, Packaging, and Orderable Information
1
Features
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Dual RF sampling 12GSPS transmit DACs
Triple RF sampling 3GSPS receive ADCs
Maximum RF signal bandwidth: 1200MHz
RF frequency range: 600MHz - 12GHz
Digital step attenuators (DSA):
TX: 40dB range, 0.125dB steps
RX: 25dB range, 0.5dB steps
Single or dual-band DUC or DDCs
16x NCOs per TX or RX
Optional Internal PLL or VCO for DAC or ADC clocks or external clock at DAC or ADC sample rate
SerDes data interface:
JESD204B and JESD204C compatible
8 SerDes transceivers up to 29.5Gbps
Subclass 1 multi-device synchronization
Package: 17mm × 17mm FCBGA, 0.8mm pitch