SBASB68 August   2025 ADS9803

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
        1. 6.3.1.1 Input Clamp Protection Circuit
        2. 6.3.1.2 Programmable Gain Amplifier (PGA)
        3. 6.3.1.3 Wide-Common-Mode Voltage Rejection Circuit
      2. 6.3.2 ADC Transfer Function
      3. 6.3.3 ADC Sampling Clock Input
      4. 6.3.4 Synchronizing Multiple ADCs
      5. 6.3.5 Reference Voltage
      6. 6.3.6 Data Interface
        1. 6.3.6.1 Data Clock Output
        2. 6.3.6.2 ADC Output Data Randomizer
        3. 6.3.6.3 Data Averaging
        4. 6.3.6.4 Test Patterns for Data Interface
          1. 6.3.6.4.1 Fixed Pattern
          2. 6.3.6.4.2 Digital Ramp
          3. 6.3.6.4.3 Alternating Test Pattern
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset
      2. 6.4.2 Power-Down
      3. 6.4.3 Initialization Sequence
      4. 6.4.4 Normal Operation
      5. 6.4.5 Speed-Boost Mode
    5. 6.5 Programming
      1. 6.5.1 Register Write
      2. 6.5.2 Register Read
      3. 6.5.3 Multiple Devices in a Daisy-Chain Topology for SPI Configuration
        1. 6.5.3.1 Register Write With Daisy-Chain
        2. 6.5.3.2 Register Read With Daisy-Chain
  8. 7 Register Map
    1. 7.1 Register Bank 0
    2. 7.2 Register Bank 1
    3. 7.3 Register Bank 2
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Parametric Measurement Unit (PMU)
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.2 Register Bank 1

Figure 7-12 Register Bank 1 Map
ADD D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0Dh RESERVED DATA_
FORMAT		 RESERVED EN_AVG RESERVED EN_MVG_AVG
12h RESERVED XOR_
PRBS		 XOR_EN RESERVED
13h RESERVED RAMP_INC_A TP_MODE_A TP_EN_A RESERVED
14h TP0_A
15h TP1_A TP0_A
16h TP1_A
18h RESERVED RAMP_INC_B TP_MODE_B TP_EN_B RESERVED
19h TP0_B
1Ah TP1_B TP0_B
1Bh TP1_B
1Ch RESERVED USER_BITS_CH[8:5] RESERVED USER_BITS_CH[4:1]
37h RESERVED BOOST_CH_SEL EN_
BOOST
3Ch RESERVED AVG_
CFG3		 RESERVED
44h USER_GAIN_CAL_CH[4:1][21:6]
45h RESERVED USER_GAIN_CAL_CH[4:1][5:0]
4Ah USER_GAIN_CAL_CH[8:5][21:6]
4Bh RESERVED USER_GAIN_CAL_CH[8:5][5:0]
92h RESERVED INIT_2 RESERVED
C0h RESERVED ANA_BW PD_CH
C1h RESERVED PD_REF RESERVED DATA_
LANES		 DATA_
RATE		 RESERVED
C2h RANGE_CH4 RANGE_CH3 RANGE_CH2 RANGE_CH1
C3h RANGE_CH8 RANGE_CH7 RANGE_CH6 RANGE_CH5
C4h RESERVED CM_RNG_CH[8:5] CM_RNG_CH[4:1] AVG_CFG2 CM_EN_CH[8:5] CM_EN_CH[4:1] AVG_
CFG1		 PD_
CHIP
C5h BOOST_CFG1 RESERVED INIT_3 PGA_
IN1T2		 RESERVED AVG_CFG4 CM_CTRL_EN BOOST_CFG2 PGA_
IN1T1		 RESERVED
Table 7-2 Register Section/Block Access Type Codes
Access Type Code Description
R R Read
W W Write
R/W R/W Read or write
Reset or Default Value
-n Value after reset or the default value

Register 0Dh (offset = Dh) [reset = 2002h]

Figure 7-13 Register 0Dh
15 14 13 12 11 10 9 8
RESERVED DATA_FORMAT RESERVED
R/W-0h R/W-1h R/W-0h
7 6 5 4 3 2 1 0
RESERVED EN_AVG RESERVED EN_MVG_AVG
R/W-0h R/W-0h R/W-1h R/W-0h
Figure 7-14 Register 0Dh Field Descriptions
Bit Field Type Reset Description
15-14 RESERVED R/W 0h Reserved. Do not change from the default reset value.
13 DATA_FORMAT R/W 1h Select data format for the ADC conversion result.
0 : Straight binary format
1 : Two's-complement format
12-7 RESERVED R/W 0h Reserved. Do not change from the default reset value.
6 EN_AVG R/W 0h Set 1b to enable data averaging. See Table 6-10 and Table 6-11 for more details.
5-1 RESERVED R/W 1h Reserved. Do not change from the default reset value.
0 EN_MVG_AVG R/W 0h Set 1b to enable moving data average. See Table 6-11 for more details.

Register 12h (offset = 12h) [reset = 2h]

Figure 7-15 Register 12h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED XOR_PRBS XOR_EN RESERVED
R/W-0h R/W-0h R/W-0h R/W-2h
Figure 7-16 Register 12h Field Descriptions
Bit Field Type Reset Description
15-5 RESERVED R/W 0h Reserved. Do not change from the default reset value.
4 XOR_PRBS R/W 0h Select bit for XOR operation when XOR_EN = 1b.
0 : PRBS is appended after the LSB of the ADC conversion result. The ADC conversion result is bit-wise XOR with the PRBS bit.
1 : The ADC conversion result is bit-wise XOR with the LSB of the ADC conversion result.
3 XOR_EN R/W 0h Enables XOR operation on the ADC conversion result.
0 : XOR operation is disabled
1 : Bit-wise XOR operation on ADC conversion result is enabled
2-0 RESERVED R/W 2h Reserved. Do not change from the default reset value.

7.2.1 Register 13h (offset = 13h) [reset = 0h]

Figure 7-17 Register 13h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RAMP_INC_A TP_MODE_A TP_EN_A RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h
Figure 7-18 Register 13h Field Descriptions
Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved. Do not change from the default reset value.
7-4 RAMP_INC_A R/W 0h Increment value for the ramp pattern output. The output ramp increments by N+1, where N is the value configured in this register.
3-2 TP_MODE_A R/W 0h Select digital test pattern for analog input channels 1, 2, 3, and 4.
0 : Fixed pattern from the TP0_A register
1 : Fixed pattern from the TP0_A register
2 : Digital ramp output
3 : Alternate fixed pattern output from the TP0_A and TP1_A registers
1 TP_EN_A R/W 0h Enable digital test pattern for data corresponding to channels 1, 2, 3, and 4.
0 : Data output is the ADC conversion result
1 : Data output is the digital test pattern for channels 1, 2, 3, and 4
0 RESERVED R/W 0h Reserved. Do not change from the default reset value.

7.2.2 Register 14h (offset = 14h) [reset = 0h]

Figure 7-19 Register 14h
15 14 13 12 11 10 9 8
TP0_A[15:0]
R/W-0h
7 6 5 4 3 2 1 0
TP0_A[15:0]
R/W-0h
Figure 7-20 Register 14h Field Descriptions
Bit Field Type Reset Description
15-0 TP0_A[15:0] R/W 0h Lower 16 bits of test pattern 0

7.2.3 Register 15h (offset = 15h) [reset = 0h]

Figure 7-21 Register 15h
15 14 13 12 11 10 9 8
TP1_A[7:0]
R/W-0h
7 6 5 4 3 2 1 0
TP0_A[23:16]
R/W-0h
Figure 7-22 Register 15h Field Descriptions
Bit Field Type Reset Description
15-8 TP1_A[7:0] R/W 0h Lower eight bits of test pattern 1
7-0 TP0_A[23:16] R/W 0h Upper eight bits of test pattern 0

7.2.4 Register 16h (offset = 16h) [reset = 0h]

Figure 7-23 Register 16h
15 14 13 12 11 10 9 8
TP1_A[23:8]
R/W-0h
7 6 5 4 3 2 1 0
TP1_A[23:8]
R/W-0h
Figure 7-24 Register 16h Field Descriptions
Bit Field Type Reset Description
15-0 TP1_A[23:8] R/W 0h Upper 16 bits of test pattern 1

Register 18h (offset = 18h) [reset = 0h]

Figure 7-25 Register 18h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RAMP_INC_B TP_MODE_B TP_EN_B RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h
Figure 7-26 Register 18h Field Descriptions
Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved. Do not change from the default reset value.
7-4 RAMP_INC_B R/W 0h Increment value for the ramp pattern output. The output ramp increments by N+1, where N is the value configured in this register.
3-2 TP_MODE_B R/W 0h Select digital test pattern for analog input channels 5, 6, 7, and 8.
0 : Fixed pattern from the TP0_B register
1 : Fixed pattern from the TP0_B register
2 : Digital ramp output
3 : Alternate fixed pattern output from the TP0_B and TP1_B registers
1 TP_EN_B R/W 0h Enable digital test pattern for data corresponding to channels 5, 6, 7, and 8.
0 : Data output is the ADC conversion result
1 : Data output is the digital test pattern
0 RESERVED R/W 0h Reserved. Do not change from the default reset value.

7.2.5 Register 19h (offset = 19h) [reset = 0h]

Figure 7-27 Register 19h
15 14 13 12 11 10 9 8
TP0_B[15:0]
R/W-0h
7 6 5 4 3 2 1 0
TP0_B[15:0]
R/W-0h
Figure 7-28 Register 19h Field Descriptions
Bit Field Type Reset Description
15-0 TP0_B[15:0] R/W 0h Lower 16 bits of test pattern 0

7.2.6 Register 1Ah (offset = 1Ah) [reset = 0h]

Figure 7-29 Register 1Ah
15 14 13 12 11 10 9 8
TP1_B[7:0]
R/W-0h
7 6 5 4 3 2 1 0
TP0_B[23:16]
R/W-0h
Figure 7-30 Register 1Ah Field Descriptions
Bit Field Type Reset Description
15-8 TP1_B[7:0] R/W 0h Lower eight bits of test pattern 1
7-0 TP0_B[23:16] R/W 0h Upper eight bits of test pattern 0

7.2.7 Register 1Bh (offset = 1Bh) [reset = 0h]

Figure 7-31 Register 1Bh
15 14 13 12 11 10 9 8
TP1_B[23:8]
R/W-0h
7 6 5 4 3 2 1 0
TP1_B[23:8]
R/W-0h
Figure 7-32 Register 1Bh Field Descriptions
Bit Field Type Reset Description
15-0 TP1_B[23:8] R/W 0h Upper 16 bits of test pattern 1

Register 1Ch (offset = 1Ch) [reset = 0h]

Figure 7-33 Register 1Ch
15 14 13 12 11 10 9 8
RESERVED USER_BITS_CH[8:5]
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED USER_BITS_CH[4:1]
R/W-0h R/W-0h
Figure 7-34 Register 1Ch Field Descriptions
Bit Field Type Reset Description
15-14 RESERVED R/W 0h Reserved. Do not change from the default reset value.
13-8 USER_BITS_CH[8:5] R/W 0h User-defined bits appended to the ADC conversion result from channels 5, 6, 7, and 8.
7-6 RESERVED R/W 0h Reserved. Do not change from the default reset value.
5-0 USER_BITS_CH[4:1] R/W 0h User-defined bits appended to the ADC conversion result from channels 1, 2, 3, and 4.

Register 37h (offset = 37h) [reset = 0h]

Figure 7-35 Register 37h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED BOOST_CH_SEL EN_BOOST
R/W-0h R/W-0h R/W-0h
Figure 7-36 Register 37h Field Descriptions
Bit Field Type Reset Description
15-3 RESERVED R/W 0h Reserved. Do not change from the default reset value.
2-1 BOOST_CH_SEL R/W 0h Select analog input channel pair for speed-boost mode.
0: CH1 and CH8
1: CH2 and CH7
2: CH3 and CH6
3: CH4 and CH5
0 EN_BOOST R/W 0h Enable speed-boost mode. See section on Speed-Boost Mode for more details.

7.2.8 Register 3Ch (offset = 3Ch) [reset = 0h]

Figure 7-37 Register 3Ch
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
AVG_CFG3 RESERVED
R/W-0h R/W-0h
Figure 7-38 Register 3Ch Field Descriptions
Bit Field Type Reset Description
15-8 RESERVED R/W 0h Reserved. Do not change from the default reset value.
7 AVG_CFG3 R/W 0h Configuration for simple averaging. See Table 6-10 for more details.
6-0 RESERVED R/W 0h Reserved. Do not change from the default reset value.

7.2.9 Register 44h (offset = 44h) [reset = 0h]

Figure 7-39 Register 44h
15 14 13 12 11 10 9 8
USER_GAIN_CAL_CH[4:1][21:6]
R/W-0h
7 6 5 4 3 2 1 0
USER_GAIN_CAL_CH[4:1][21:6]
R/W-0h
Figure 7-40 Register 44 Field Descriptions
Bit Field Type Reset Description
15-0 USER_GAIN_CAL_CH[4:1][21:6] R/W 0h 21-bit gain error correction code for ADC A

7.2.10 Register 45h (offset = 45h) [reset = 0h]

Figure 7-41 Register 45h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED USER_GAIN_CAL_CH[4:1][5:0]
R/W-0h R/W-0h
Figure 7-42 Register 45h Field Descriptions
Bit Field Type Reset Description
15-6 RESERVED R/W 0h Reserved. Do not change from the default reset value.
5-0 USER_GAIN_CAL_CH[4:1][5:0] R/W 0h 21-bit gain error correction code for ADC A.

7.2.11 Register 4Ah (offset = 4Ah) [reset = 0h]

Figure 7-43 Register 4Ah
15 14 13 12 11 10 9 8
USER_GAIN_CAL_CH[8:5][21:6]
R/W-0h
7 6 5 4 3 2 1 0
USER_GAIN_CAL_CH[8:5][21:6]
R/W-0h
Figure 7-44 Register 4Ah Field Descriptions
Bit Field Type Reset Description
15-0 USER_GAIN_CAL_CH[8:5][21:6] R/W 0h 21-bit gain error correction code for ADC B.

Register 4Bh (offset = 4Bh) [reset = 0h]

Figure 7-45 Register 4Bh
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED USER_GAIN_CAL_CH[8:5][5:0]
R/W-0h R/W-0h
Figure 7-46 Register 4Bh Field Descriptions
Bit Field Type Reset Description
15-6 RESERVED R/W 0h Reserved. Do not change from the default reset value.
5-0 USER_GAIN_CAL_CH[8:5][5:0] R/W 0h 21-bit gain error correction code for UADC B.

Register 92h (offset = 92h) [reset = 0h]

Figure 7-47 Register 92h
15 14 13 12 11 10 9 8
RESERVED
R/W-0h
7 6 5 4 3 2 1 0
RESERVED INIT_2 RESERVED
R/W-0h R/W-0h R/W-0h
Figure 7-48 Register 92h Field Descriptions
Bit Field Type Reset Description
15-2 RESERVED R/W 0h Reserved. Do not change from the default reset value.
1 INIT_2 R/W 0h Set to 1b for normal operation. Refer to section on Initialization Sequence for more details.
0 RESERVED R/W 0h Reserved. Do not change from the default reset value.

7.2.12 Register C0h (offset = C0h) [reset = 0h]

Figure 7-49 Register C0h
15 14 13 12 11 10 9 8
RESERVED ANA_BW
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
ANA_BW PD_CH
R/W-0h R/W-0h
Figure 7-50 Register C0h Field Descriptions
Bit Field Type Reset Description
15-10 RESERVED R/W 0h Reserved. Do not change from the default reset value.
9-2 ANA_BW R/W 0h Select analog input bandwidth for the respective analog input channels.
MSB = BW control for channel 8
LSB = BW control for channel 1
0 : Low-noise mode
1 : Wide-bandwidth mode
1-0 PD_CH R/W 0h Power-down control for the analog input channels.
0 : Normal operation
1 : Channels 5, 6, 7, and 8 powered down
2 : Channels 1, 2, 3, and 4 powered down
3 : All channels powered down

7.2.13 Register C1h (offset = C1h) [reset = 0h]

Figure 7-51 Register C1h
15 14 13 12 11 10 9 8
RESERVED PD_REF RESERVED DATA_LANES DATA_RATE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED
R/W-0h
Figure 7-52 Register C1h Field Descriptions
Bit Field Type Reset Description
15-12 RESERVED R/W 0h Reserved. Do not change from the default reset value.
11 PD_REF R/W 0h ADC reference voltage source selection.
0 : Internal reference enabled.
1 : Internal reference disabled. Connect the external reference voltage to the REFIO pin.
10 RESERVED R/W 0h Reserved. Do not change from the default reset value.
9 DATA_LANES R/W 0h Select number of output data lanes per ADC channel.
0 : 4-lane mode. CH[4:1] data are output on pins D3 and D2. CH[8:5] data are output on pins D1 and D0.
1 : 2-lane mode. CH[4:1] data are output on pin D3. CH[8:5] data are output on pin D1.
8 DATA_RATE R/W 0h Select data rate for the data interface.
0 : Double data rate (DDR)
1 : Single data rate (SDR)
7-0 RESERVED R/W 0h Reserved. Do not change from the default reset value.

7.2.14 Register C2h (offset = C2h) [reset = 0h]

Figure 7-53 Register C2h
15 14 13 12 11 10 9 8
RANGE_CH4 RANGE_CH3
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RANGE_CH2 RANGE_CH1
R/W-0h R/W-0h
Figure 7-54 Register C2h Field Descriptions
Bit Field Type Reset Description
15-12 RANGE_CH4 R/W 0h Select the analog input voltage range.
0 : ±5V
1 : ±3.5V
2 : ±2.5V
3 : ±7V
4 : ±10V
5 : ±12V
11-8 RANGE_CH3 R/W 0h
7-4 RANGE_CH2 R/W 0h
3-0 RANGE_CH1 R/W 0h

7.2.15 Register C3h (offset = C3h) [reset = 0h]

Figure 7-55 Register C3h
15 14 13 12 11 10 9 8
RANGE_CH8 RANGE_CH7
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RANGE_CH6 RANGE_CH5
R/W-0h R/W-0h
Figure 7-56 Register C3h Field Descriptions
Bit Field Type Reset Description
15-12 RANGE_CH8 R/W 0h Select the analog input voltage range.
0 : ±5V
1 : ±3.5V
2 : ±2.5V
3 : ±7V
4 : ±10V
5 : ±12V
11-8 RANGE_CH7 R/W 0h
7-4 RANGE_CH6 R/W 0h
3-0 RANGE_CH5 R/W 0h

Register C4h (offset = C4h) [reset = 0h]

Figure 7-57 Register C4h
15 14 13 12 11 10 9 8
RESERVED CM_RNG_CH[8:5]
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
CM_RNG_CH[4:1] AVG_CFG2 CM_EN_
CH[8:5]		 CM_EN_
CH[4:1]		 AVG_CFG1 PD_CHIP
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Figure 7-58 Register C4h Field Descriptions
Bit Field Type Reset Description
15-10 RESERVED R/W 0h Reserved. Do not change from the default reset value.
9-8 CM_RNG_CH[8:5] R/W 0h CM_RNG_CH[4:1] sets the common-mode range for channels 1, 2, 3, and 4.
CM_RNG_CH[8:5] sets the common-mode range for channels 5, 6, 7, and 8.
0 : CM range is equal to ±RANGE / 2
1 : CM range is equal to ±6V
2 : CM range is equal to ±12V
7-6 CM_RNG_CH[4:1] R/W 0h
5-4 AVG_CFG2 R/W 0h Configuration for simple averaging. See Table 6-10 for more details.
3 CM_EN_CH[8:5] R/W 0h CM_EN_CH[4:1] enables wide common-mode range control for channels 1 to 4.
CM_EN_CH[8:5] enables the wide common-mode range control for channels 5 to 8.
0 : Wide common-mode range control disabled
1 : Wide common-mode range control enabled
2 CM_EN_CH[4:1] R/W 0h
1 AVG_CFG1 R/W 0h Configuration for simple averaging. See Table 6-10 for more details.
0 PD_CHIP R/W 0h Full chip power-down control.
0 : Normal device operation
1 : Full device powered-down

7.2.16 Register C5h (offset = C5h) [reset = 0h]

Figure 7-59 Register C5h
15 14 13 12 11 10 9 8
BOOST_CFG1 RESERVED INIT_3 PGA_INIT2 RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED AVG_CFG4 CM_CTRL_EN BOOST_CFG2 PGA_INIT2 RESERVED
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Figure 7-60 Register C5h Field Descriptions
Bit Field Type Reset Description
15-14 BOOST_CFG1 R/W 0h Configuration for speed-boost mode. See Table 6-15 for more details.
13-11 RESERVED R/W 0h Reserved. Do not change from the default reset value.
10 INIT_3 R/W 0h Set to 1 for normal operation. Refer to Initialization Sequence for more details.
9 PGA_INIT2 R/W 0h Conifguration for PGA initialization. Set to 1 for normal operation. Refer to Initialization Sequence for more details.
8-7 RESERVED R/W 0h Reserved. Do not change from the default reset value.
6-5 AVG_CFG4 R/W 0h Configuration for simple averaging. See Table 6-10 for more details.
4 CM_CTRL_EN R/W 0h Enable the wide common-mode range control for all analog input channels.
0 : CM range for all analog input channels is ±12V
1 : CM range is user-defined in the CM_EN_CH[4:1], CM_EN_CH[8:5], CM_RNG_CH[4:1], and CM_RNG_CH[8:5] registers
3 BOOST_CFG2 R/W 0h Configuration for speed-boost mode. See Table 6-15 for more details.
2 PGA_INIT1 R/W 0h Conifguration for PGA initialization. Set to 1 for normal operation. Refer to Initialization Sequence for more details.
1-0 RESERVED R/W 0h Reserved. Do not change from the default reset value.