SBASBC4 December   2025 ADS8688W

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Analog Input Impedance
      3. 7.3.3  Input Overvoltage Protection Circuit
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  Second-Order, Low-Pass Filter (LPF)
      6. 7.3.6  ADC Driver
      7. 7.3.7  Multiplexer (MUX)
      8. 7.3.8  Reference
        1. 7.3.8.1 Internal Reference
        2. 7.3.8.2 External Reference
      9. 7.3.9  Auxiliary Channel
        1. 7.3.9.1 Input Driver for the AUX Channel
      10. 7.3.10 ADC Transfer Function
      11. 7.3.11 Alarm Feature
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Interface
        1. 7.4.1.1 Digital Pin Description
          1. 7.4.1.1.1 CS (Input)
          2. 7.4.1.1.2 SCLK (Input)
          3. 7.4.1.1.3 SDI (Input)
          4. 7.4.1.1.4 SDO (Output)
          5. 7.4.1.1.5 DAISY (Input)
          6. 7.4.1.1.6 RST / PD (Input)
        2. 7.4.1.2 Data Acquisition Example
        3. 7.4.1.3 Host-to-Device Connection Topologies
          1. 7.4.1.3.1 Daisy-Chain Topology
          2. 7.4.1.3.2 Star Topology
      2. 7.4.2 Device Modes
        1. 7.4.2.1 Continued Operation in the Selected Mode (NO_OP)
        2. 7.4.2.2 Frame Abort Condition (FRAME_ABORT)
        3. 7.4.2.3 STANDBY Mode (STDBY)
        4. 7.4.2.4 Power-Down Mode (PWR_DN)
        5. 7.4.2.5 Auto Channel Enable With Reset (AUTO_RST)
        6. 7.4.2.6 Manual Channel n Select (MAN_Ch_n)
        7. 7.4.2.7 Channel Sequencing Modes
        8. 7.4.2.8 Reset Program Registers (RST)
  9. 8 Register Maps
    1. 8.1 Command Register Description
    2. 8.2 Program Register Description
      1. 8.2.1 Program Register Read/Write Operation
      2. 8.2.2 Program Register Map
        1. 8.2.2.1 Auto-Scan Sequencing Control Registers
          1. 8.2.2.1.1 Auto-Scan Sequence Enable Register (address = 01h)
          2. 8.2.2.1.2 Channel Power Down Register (address = 02h)
        2. 8.2.2.2 Alarm Flag Registers (Read-Only)
          1. 8.2.2.2.1 ALARM Overview Tripped-Flag Register (address = 10h)
          2. 8.2.2.2.2 Alarm Flag Registers: Tripped and Active (address = 11h to 14h)
          3. 8.2.2.2.3 Alarm Threshold Setting Registers
        3. 8.2.2.3 Device Features Selection Control Register (address = 03h)
        4. 8.2.2.4 Range Select Registers (addresses 05h-0Ch)
        5. 8.2.2.5 Command Read-Back Register (address = 3Fh)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Phase-Compensated, 8-Channel, Multiplexed Data Acquisition System for Power Automation
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 78
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
8.2.2.2.3 Alarm Threshold Setting Registers

The ADS8688W feature individual high and low alarm threshold settings for each channel. Each alarm threshold is 16 bits wide with 8-bit hysteresis, which is the same for both high and low threshold settings. This 40-bit setting is accomplished through five 8-bit registers associated with every high and low alarm.

NAME(1)ADDRBIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
Ch 0 Hysteresis15hCH0_HYST[5:0]00
Ch 0 High Threshold MSB16hCH0_HT[13:6]
Ch 0 High Threshold LSB17hCH0_HT[5:0]00
Ch 0 Low Threshold MSB18hCH0_LT[13:6]
Ch 0 Low Threshold LSB19hCH0_LT[5:0]00
Ch 1 Hysteresis1AhCH1_HYST[5:0]00
Ch 1 High Threshold MSB1BhCH1_HT[13:6]
Ch 1 High Threshold LSB1ChCH1_HT[5:0]00
Ch 1 Low Threshold MSB1DhCH1_LT[13:6]
Ch 1 Low Threshold LSB1EhCH1_LT[5:0]00
Ch 2 Hysteresis1FhCH2_HYST[5:0]00
Ch 2 High Threshold MSB20hCH2_HT[13:6]
Ch 2 High Threshold LSB21hCH2_HT[5:0]00
Ch 2 Low Threshold MSB22hCH2_LT[13:6]
Ch 2 Low Threshold LSB23hCH2_LT[5:0]00
Ch 3 Hysteresis24hCH3_HYST[5:0]00
Ch 3 High Threshold MSB25hCH3_HT[13:6]
Ch 3 High Threshold LSB26hCH3_HT[5:0]00
Ch 3 Low Threshold MSB27hCH3_LT[13:6]
Ch 3 Low Threshold LSB28hCH3_LT[5:0]00
Ch 4 Hysteresis(1)29hCH4_HYST[5:0]00
Ch 4 High Threshold MSB2AhCH4_HT[13:6]
Ch 4 High Threshold LSB2BhCH4_HT[5:0]00
Ch 4 Low Threshold MSB2ChCH4_LT[13:6]
Ch 4 Low Threshold LSB2DhCH4_LT[5:0]00
Ch 5 Hysteresis2EhCH5_HYST[5:0]00
Ch 5 High Threshold MSB2FhCH5_HT[13:6]
Ch 5 High Threshold LSB30hCH5_HT[5:0]00
Ch 5 Low Threshold MSB31hCH5_LT[13:6]
Ch 5 Low Threshold LSB32hCH5_LT[5:0]00
Ch 6 Hysteresis33hCH6_HYST[5:0]00
Ch 6 High Threshold MSB34hCH6_HT[13:6]
Ch 6 High Threshold LSB35hCH6_HT[5:0]00
Ch 6 Low Threshold MSB36hCH6_LT[13:6]
Ch 6 Low Threshold LSB37hCH6_LT[5:0]00
Ch 7 Hysteresis38hCH7_HYST[5:0]00
Ch 7 High Threshold MSB39hCH7_HT[13:6]
Ch 7 High Threshold LSB3AhCH7_HT[5:0]00
Ch 7 Low Threshold MSB3BhCH7_LT[13:6]
Ch 7 Low Threshold LSB3ChCH7_LT[5:0]00
(1) Shading indicates bits or registers not included in the 4-channel version of the device.
Figure 8-10 Ch n Hysteresis Registers
76543210
CHn_HYST[5:0]00
R/W-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-12 Channel n Hysteresis Register Field Descriptions
(n = 0 to 7 for the ADS8688W; n = 0 to 3 for the ADS8684W)
BitFieldTypeResetDescription
7-0Channel n Hysteresis[7-0]
(n = 0 to 7 for the ADS8688W;
n = 0 to 3 for the ADS8684W)		R/W0hThese bits set the channel high and low alarm hysteresis for channel n(n = 0 to 7 for the ADS8688W; n = 0 to 3 for the ADS8684W)
For example, bits 7-0 of the channel 0 register (address 15h) set the channel 0 alarm hysteresis.

00000000 = No hysteresis

00000001 = ±1LSB hysteresis

00000010 to 11111110 = ±2LSB to ±62LSB hysteresis

11111111 = ±63LSB hysteresis

Figure 8-11 Ch n High Threshold MSB Registers
76543210
CHn_HT[15:8]
R/W-1h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-13 Channel n High Threshold MSB Register Field Descriptions
(n = 0 to 7 for the ADS8688W; n = 0 to 3 for the ADS8684W)
BitFieldTypeResetDescription
7-0CHn_HT[15:8]
(n = 0 to 7 for the ADS8688W;
n = 0 to 3 for the ADS8684W)		R/W1hThese bits set the MSB byte for the 16-bit channel n high alarm.
For example, bits 7-0 of the channel 0 register (address 16h) set the MSB byte for the channel 0 high alarm threshold. The channel 0 high alarm threshold is AAFFh when bits 7-0 of the ch 0 high threshold MSB register (address 16h) are set to AAh and bits 7-0 of the ch 0 high threshold LSB register (address 17h) are set to FFh.
0000 0000 = MSB byte is 00h
0000 0001 = MSB byte is 01h
0000 0010 to 1110 1111 = MSB byte is 02h to FEh
1111 1111 = MSB byte is FFh
Figure 8-12 Ch n High Threshold LSB Registers
76543210
CHn_HT[7:0]
R/W-1hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-14 Channel n High Threshold LSB Register Field Descriptions
(n = 0 to 7 for the ADS8688W; n = 0 to 3 for the ADS8684W)
BitFieldTypeResetDescription
7-0CHn_HT[7-0]
(n = 0 to 7 for the ADS8688W;
n = 0 to 3 for the ADS8684W)		R/W1hThese bits set the LSB for the 16-bit channel n high alarm.
For example, bits 7-0 of the channel 0 register (address 17h) set the LSB for the channel 0 high alarm threshold. The channel 0 high alarm threshold is AAFFh when bits 7-0 of the ch 0 high threshold MSB register (address 16h) are set to AAh and bits 7-0 of the ch 0 high threshold LSB register (address 17h) are set to FFh.

0000 0000 = LSB is 00h

0000 0001 = LSB is 01h

0000 0010 to 1111 1110 = LSB is 02h to FEh

1111 1111 = LSB byte is FFh

Figure 8-13 Ch n Low Threshold MSB Registers
76543210
CHn_LT[15:8]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-15 Channel n Low Threshold MSB Register Field Descriptions
(n = 0 to 7 for the ADS8688W; n = 0 to 3 for the ADS8684W)
BitFieldTypeResetDescription
7-0CHn_LT[15:8]
(n = 0 to 7 for the ADS8688W;
n = 0 to 3 for the ADS8684W)		R/W0hThese bits set the MSB byte for the 16-bit channel n low alarm.
For example, bits 7-0 of the channel 0 register (address 18h) set the MSB byte for the channel 0 low alarm threshold. The channel 0 low alarm threshold is AAFFh when bits 7-0 of the ch 0 low threshold MSB register (address 18h) are set to AAh and bits 7-0 of the ch 0 low threshold LSB register (address 19h) are set to FFh.
0000 0000 = MSB byte is 00h
0000 0001 = MSB byte is 01h
0000 0010 to 1110 1111 = MSB byte is 02h to FEh
1111 1111 = MSB byte is FFh
Figure 8-14 Ch n Low Threshold LSB Registers
76543210
CHn_LT[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-16 Channel n Low Threshold MSB Register Field Descriptions
(n = 0 to 7 for the ADS8688W; n = 0 to 3 for the ADS8684W)
BitFieldTypeResetDescription
7-0CHn_LT[7-0]
(n = 0 to 7 for the ADS8688W; n = 0 to 3 for the ADS8684W)		R/W0hThese bits set the LSB for the 16-bit channel n low alarm.
For example, bits 7-0 of the channel 0 register (address 19h) set the LSB for the channel 0 low alarm threshold. The channel 0 low alarm threshold is AAFFh when bits 7-0 of the ch 0 low threshold MSB register (address 18h) are set to AAh and bits 7-0 of the ch 0 low threshold LSB register (address 19h) are set to FFh.

0000 0000 = LSB byte is 00h

0000 0001 = LSB byte is 01h

0000 0010 to 1110 1111 = LSB byte is 02h to FEh

1111 1111 = LSB byte is FFh