SBAU407 april   2023 ADS8354

 

  1.   Abstract
  2.   Trademarks
  3. 1Overview
    1. 1.1 ADS8354EVM-PDK Features
    2. 1.2 ADS8354EVM Features
    3. 1.3 Related Documentation From Texas Instruments
  4. 2Analog Interface
    1. 2.1 Connectors for Analog Inputs
    2. 2.2 ADC Input Signal Driver
      1. 2.2.1 Input Signal Path
  5. 3Digital Interfaces
    1. 3.1 SPI for the ADC Digital I/O
  6. 4Power Supplies
    1. 4.1 ADC Input Driver Configuration
    2. 4.2 ADC Voltage Reference Configuration
  7. 5ADS8354EVM-PDK Initial Setup
    1. 5.1 Default Jumper Settings
    2. 5.2 EVM Graphical User Interface Software Installation
  8. 6ADS8354EVM-PDK Operation
    1. 6.1 EVM GUI Global Settings for ADC Control
    2. 6.2 Time Domain Display Tool
    3. 6.3 Spectral Analysis Tool
    4. 6.4 Histogram Analysis Tool
  9. 7Bill of Materials, Printed-Circuit Board Layout, and Schematics
    1. 7.1 Bill of Materials
    2. 7.2 PCB Layout
    3. 7.3 Schematics

EVM GUI Global Settings for ADC Control

Figure 6-3 shows the input parameters of the GUI (and the default values), through which the various functions of the ADS8354EVM-PDK can be exercised. These settings are global and persist across the GUI tools listed in the top left pane (or from one page to another).

GUID-20230223-SS0I-T9XF-CNLT-V7HLRLRJWQ95-low.svgFigure 6-3 EVM GUI Global Input Parameters

The ADS8354 interface configurations can be selected on this page. The GUI lets the user select the ADC input range, ADC INM input configuration, ADC voltage reference, and ADC data format using a drop-down menu.

The SCLK Frequency and Sampling Rate are selected on this page. The GUI lets the user enter the target values for these two parameters, and the GUI computes the closest value that can be achieved, considering the timing constraints of the device.

Select either one of the ADCs or both of the ADCs if they are configured in the simultaneous-sampling scheme described in Section 2.1 by clicking on the drop-down menu titled Channel Modes. Specify a target SCLK frequency (Hz) and the GUI tries to match this frequency as closely as possible by changing the PHI PLL settings; however, the achievable frequency can differ from the target value entered. Similarly, the sampling rate of the ADC can be adjusted by modifying the Target Sampling Rate argument (Hz). The achievable ADC sampling rate can differ from the target value, depending on the applied SCLK frequency and the closest match achievable is displayed. This page, therefore, allows various settings available on the device to be tested in a repetitive fashion until arriving at the best settings for the corresponding test scenario.