SBOA212A January   2018  – January 2019 OPA2353 , OPA2365 , OPA353 , OPA365 , TLV3502

 

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  3.   Revision History

Design Goals

InputOutputSupply
ViMinViMaxVoMinVoMaxVccVeeVref
–2.0 V2.0 V0 V5 V5 V0 V2.5 V

Design Description

This circuit utilizes a triangle wave generator and comparator to generate a 500 kHz pulse-width-modulated (PWM) waveform with a duty cycle that is inversely proportional to the input voltage. An op amp and comparator (U3 and U4) generate a triangle waveform which is applied to the inverting input of a second comparator (U2). The input voltage is applied to the non-inverting input of U2. By comparing the input waveform to the triangle wave, a PWM waveform is produced. U2 is placed in the feedback loop of an error amplifier (U1) to improve the accuracy and linearity of the output waveform.

GUID-BBDD843D-1BFC-4529-9350-8314EC0787AC-low.gif

Design Notes

  1. Use a comparator with push-pull output and minimal propagation delay.
  2. Use an op amp with sufficient slew rate, GBW, and voltage output swing.
  3. Place the pole created by C1 below the switching frequency and well above the audio range.
  4. Vref must be low impedance (for example, output of an op amp).

Design Steps

  1. Set the error amplifier inverting signal gain.
    Gain = R 4 R 3 = 1 V V
    Select  R 3 = R 4 = 10
  2. Determine R1 and R2 to divide Vref to cancel the non-inverting gain.
    V o_dc = 1 + R 4 R 3 R 2 R 1 + R 2 × Vref
    R 1 = R 2 = R 3 = R 4 = 10 V o_dc = 2 . 5 V
  3. The amplitude of Vtri must be chosen such that it is greater than the maximum amplitude of Vi (2.0 V) to avoid 0% or 100% duty cycle in the PWM output signal. Select Vtri to be 2.1 V. The amplitude of V1 = 2.5 V.
    V tri  (Amplitude) = R 5 R 6 × V 1 ( Amplitude )
    Select  R 6  to be  10 ,   then compute  R 5
    R 5 = V tri ( Amplitude ) × R 6 V 1   ( Amplitude ) = 8 . 4 8 . 45  (Standard Value)
  4. Set the oscillation frequency to 500 kHz.
    f t = R 6 4 × R 7 × R 5 × C 3
    Set  C 3 = 100 pF ,  then compute  R 7
    R 7 = R 6 4 × f t × R 5 × C 3 = 5 . 92 5 . 90  (Standard Value)
  5. Choose C1 to limit amplifier bandwidth to below switching frequency.
    f p = 1 2 × π × R 4 × C 1
    C 1 = 100 pF f p = 159 kHz
  6. Select C2 to filter noise from Vref.
C2=100nF (Standard Value)
fdiv=12×π×C2×R1×R2 R1+R2 =320Hz

Design Simulations

DC Simulation Results

GUID-382692E5-CDA7-4BFD-8892-71CB3D148046-low.gif

Transient Simulation Results

GUID-49199EF1-4E47-4922-957E-DA6D5C4811F5-low.gif

Design References

See Analog Engineer's Circuit Cookbooks for TI's comprehensive circuit library.

See circuit SPICE simulation file SBOC502.

See TIPD108, Analog PWM Generator 5V, 500 kHz PWM Output

Design Featured Op Amp

OPA2365
Vss 2.2 V to 5.5 V
VinCM Rail-to-rail
Vout Rail-to-rail
Vos 100 µV
Iq 4.6 mA
Ib 2 pA
UGBW50 MHz
SR25 V/µs
#Channels2
OPA2365

Design Comparator

TLV3502
Vss 2.2 V to 5.5 V
VinCM Rail-to-rail
Vout Rail-to-rail
Vos 1 mV
Iq 3.2 mA
Ib 2 pA
UGBW
SR
#Channels2
TLV3502

Design Alternate Op Amp

OPA2353
Vss 2.7 V to 5.5 V
VinCM Rail-to-rail
Vout Rail-to-rail
Vos 3 mV
Iq 5.2 mA
Ib 0.5 pA
UGBW44 MHz
SR22 V/µs
#Channels2
OPA2352