SBOA212B January   2018  – October 2024 OPA2353 , OPA2365 , OPA353 , OPA365 , TLV3502

 

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  3.   Trademarks
  4.   Revision History

Design Goals

Input Output Supply
ViMin ViMax VoMin VoMax Vcc Vee Vref
–2.0V 2.0V 0V 5V 5V 0V 2.5V

Design Description

This circuit utilizes a triangle wave generator and comparator to generate a 500kHz pulse-width-modulated (PWM) waveform with a duty cycle that is inversely proportional to the input voltage. An op amp and comparator (U3 and U4) generate a triangle waveform which is applied to the inverting input of a second comparator (U2). The input voltage is applied to the non-inverting input of U2. By comparing the input waveform to the triangle wave, a PWM waveform is produced. U2 is placed in the feedback loop of an error amplifier (U1) to improve the accuracy and linearity of the output waveform.

Design Notes

  1. Use a comparator with push-pull output and minimal propagation delay.
  2. Use an op amp with sufficient slew rate, GBW, and voltage output swing.
  3. Place the pole created by C1 below the switching frequency and well above the audio range.
  4. Vref must be low impedance (for example, output of an op amp).

Design Steps

  1. Set the error amplifier inverting signal gain.
    Gain = R 4 R 3 = 1 V V
    Select  R 3 = R 4 = 10
  2. Determine R1 and R2 to divide Vref to cancel the non-inverting gain.
    V o_dc = 1 + R 4 R 3 R 2 R 1 + R 2 × Vref
    R 1 = R 2 = R 3 = R 4 = 10 V o_dc = 2 . 5 V
  3. The amplitude of Vtri must be chosen such that it is greater than the maximum amplitude of Vi (2.0V) to avoid 0% or 100% duty cycle in the PWM output signal. Select Vtri to be 2.1V. The amplitude of V1 = 2.5V.
    V tri  (Amplitude) = R 5 R 6 × V 1 ( Amplitude )
    Select  R 6  to be  10 ,   then compute  R 5
    R 5 = V tri ( Amplitude ) × R 6 V 1   ( Amplitude ) = 8 . 4 8 . 45  (Standard Value)
  4. Set the oscillation frequency to 500kHz.
    f t = R 6 4 × R 7 × R 5 × C 3
    Set  C 3 = 100 pF ,  then compute  R 7
    R 7 = R 6 4 × f t × R 5 × C 3 = 5 . 92 5 . 90  (Standard Value)
  5. Choose C1 to limit amplifier bandwidth to below switching frequency.
    f p = 1 2 × π × R 4 × C 1
    C 1 = 100 pF f p = 159 kHz
  6. Select C2 to filter noise from Vref.
    C 2 = 100 nF  (Standard Value)
    f div = 1 2 × π × C 2 × R 1 × R 2 R 1 + R 2 = 320 Hz

Design Simulations

DC Simulation Results

Transient Simulation Results

Design References

Texas Instruments, Simulation for PWM Generator Circuit, circuit SPICE simulation file

Texas Instruments, Analog PWM Generator 5V, 500kHz PWM Output, reference design

Design Featured Op Amp

OPA2365
Vss 2.2V to 5.5V
VinCM Rail-to-rail
Vout Rail-to-rail
Vos 100µV
Iq 4.6mA
Ib 2pA
UGBW 50MHz
SR 25V/µs
#Channels 2
OPA2365

Design Comparator

TLV3502
Vss 2.2V to 5.5V
VinCM Rail-to-rail
Vout Rail-to-rail
Vos 1mV
Iq 3.2mA
Ib 2pA
UGBW
SR
#Channels 2
TLV3502

Design Alternate Op Amp

OPA2353
Vss 2.7V to 5.5V
VinCM Rail-to-rail
Vout Rail-to-rail
Vos 3mV
Iq 5.2mA
Ib 0.5pA
UGBW 44MHz
SR 22V/µs
#Channels 2
OPA2352