SBOA256A December   2018  – October 2024 OPA374 , TLV9061

 

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  3.   Trademarks

Design Goals

Diff. Input Vi Diff. Output (Vo1 – Vo2) Supply
ViMin ViMax VoMin VoMax Vcc Vee Vref
–500mV +500mV –2.5V +2.5V +5 0V +2.5V
Lower Cutoff Freq. Upper Cutoff Freq.
16Hz > 1MHz

Design Description

This circuit uses two op amps to build a discrete, single-supply diff-in diff-out amplifier. The circuit converts a differential signal to a differential output signal.

Design Notes

  1. Verify that R1 and R2 are well matched with high accuracy resistors to maintain high DC common-mode rejection performance.
  2. Increase R4 and R5 to match the necessary input impedance at the expense of thermal noise performance.
  3. Bias for single-supply operation can also be created by a voltage divider from Vcc to ground.
  4. Vref sets the output voltage of the instrumentation amplifier bias at mid-supply to allow the output to swing to both supply rails.
  5. Choose C1 and C2 to select the lower cutoff frequency.
  6. Linear operation is contingent upon the input common-mode and the output swing ranges of the discrete op amps used. The linear output swing ranges are specified under the Aol test conditions in the op amps data sheets

Design Steps

  1. The transfer function of the circuit is shown below.
    V oDiff = V i × G + V ref where   V i = the   differential   input   voltage V ref = the   reference   voltage   provided   to   the   amplifier G = 1 + 2 × ( R 1 R 3 )  
  2. Choose resistors R1 = R2 to maintain common-mode rejection performance.
    Choose   R 1 = R 2 = 20    ( Standard   value )
  3. Choose resistors R4 and R5 to meet the desired input impedance.
    Choose   R 4 = R 5 = 10    ( Standard   value )
  4. Calculate R3 to set the differential gain.
    Gain = 1 + ( 2 × R 1 R 3 ) = V V R 1   = R 2 =   20  k G = 1 + 2 × 20  R 3 = V V V V - 1 = 40  R 3 = 4 R 3 = 40  4 = 10    ( Standard   value )
  5. Set the reference voltage Vref at mid-supply.
    V ref = V cc 2 = V 2 V ref = 2 . 5 V
  6. Calculate C1 and C2 to set the lower cutoff frequency.
    f c = 1 2 × π × R 4 × C 1 = 16  Hz R 4 = R 5 = 10  f c = 1 2 × π × 10  × C 1 = 16  Hz C 1 = 1 2 × π × 10  × 16  Hz = 0 . 99 μF C 1 = C 2 = 1 μF   ( Standard   value )

Design Simulations

AC Simulation Results

In the following figure, notice the lower –3-dB cutoff frequency is approximately 16Hz and the upper cutoff frequency is > 1MHz as required for this design.

Transient Simulation Results

References

Texas Instruments, SBOMAU5 SPICE Simulation, file download

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