SBOA542 November   2022 TMP1826 , TMP1827

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
    1. 1.1 Bus Reset and Response
    2. 1.2 Host Write, Device Read
    3. 1.3 Host Read, Device Write
  4. 2Interfacing TMP1826 With the Host MCU
    1. 2.1 Using GPIO as Host Interface
    2. 2.2 Software Driver for GPIO
    3. 2.3 Using UART as Host Interface
    4. 2.4 Software Driver for UART
    5. 2.5 Using SPI as Host Interface
    6. 2.6 Software Driver for SPI
  5. 3Summary
  6. 4References

1.1 Bus Reset and Response

All communication to the TMP1826 on the single-wire begins with the bus reset and response phase. The phase is initiated by the host by holding the single-wire data line low for a period of tRSTL. All devices on the bus, irrespective of their current state respond to the bus reset, by reinitializing their internal state and responding to the host-initiated bus reset. The devices respond after a minimum of tPDH, by holding the single-wire low for a time period of tRSTH as shown in Figure 1-2.

Figure 1-2 Bus Reset and Response