SBOK044B December   2020  – December 2024 TPS7H4010-SEP

 

  1.   1
  2. 1 Abstract
  3.   Trademarks
  4. 2 Introduction
  5. 3 Single-Event Effects (SEE)
  6. 4 Device and Test Board Information
  7. 5 Irradiation Facility and Setup
  8. 6 Depth, Range, and LETEFF Calculation
  9. 7 Test Setup and Procedures
  10. 8 Destructive Single-Event Effects (DSEE)
    1. 8.1 Single-Event Latch-up (SEL) Results
    2. 8.2 Single-Event Burnout (SEB) and Single-Event Gate Rupture (SEGR) Results
  11. 9 Single-Event Transients (SET)
  12. 10Event Rate Calculations
  13. 11Summary
  14. 12Revision History
  15.   A Total Ionizing Dose from SEE Experiments
  16.   B References

3 Single-Event Effects (SEE)

The primary concern for the TPS7H4010-SEP is the robustness against destructive single-event effects (DSEE): single-event latch-up (SEL), single-event burnout (SEB), and single-event gate rupture (SEGR). In mixed technologies such as the BiCMOS process used on the TPS7H4010-SEP, the CMOS circuitry introduces a potential for SEL susceptibility.

SEL can occur if excess current injection caused by the passage of an energetic ion is high enough to trigger the formation of a parasitic cross-coupled PNP and NPN bipolar structure (formed between the p-sub and n-well and n+ and p+ contacts) [1,2]. The parasitic bipolar structure initiated by a single-event creates a high-conductance path (inducing a steady-state current that is typically orders-of-magnitude higher than the normal operating current) between power and ground that persists (is “latched”) until power is removed, the device is reset, or until the device is destroyed by the high-current state. The TPS7H4010-SEP was tested for SEL at the maximum recommended voltage of 32 V, maximum load current of 6 A, and VOUT of 3.3 and 1.8 V. The device exhibited no SEL with heavy-ions with LETEFF = 43 MeV·cm2/mg at flux ≈105 ions/cm2·s, fluences of ≈107 ions/cm2, and a die temperature of 125°C.

Since this device is designed to conduct large currents (up to 6 A) and withstand up to 32 V during the off-state, the power LDMOS introduces a potential susceptibility for SEB and SEGR [2]. The TPS7H4010-SEP was evaluated for SEB/SEGR at full load conditions of 6 A, and a maximum voltage of 32 V in both the enabled and disabled modes. Because it has been shown that MOSFET susceptibility to burnout decreases with temperature [2], the device was evaluated while operating under sub-ambienttemperatures. The devices were cooled-down (or "chilled") by using VORTEC tube (model 611). During the SEB/SEGR testing, not a single current event was observed, demonstrating that the TPS7H4010-SEP is SEB/SEGR-free up to LETEFF = 43 MeV·cm2/mg at a flux of ≈105 ions/cm2·s, fluences of ≈107 ions/cm2, and a die temperature of ≈10°C.

The TPS7H4010-SEP was characterized for SET and SEFIs at flux of ≈104 ions/cm2·s, fluences of 3 × 106 ions/cm2, at room temperature. The device was characterized at PVIN = 12 V to VOUT = 3.3 V and PVIN = 5 V to VOUT = 1.8 V at full load of 6-A. Under these conditions the device showed 2 different single-event transients (SET) signatures and 1 single-event functional interrupt (SEFI) under heavy-ion irradiation. All observed types of SETs were self-recoverable without the need of external intervention. The observed transients can be classified as:

  1. A brief transient of the output voltage (refer here as VOUTSET). For the purpose of this report the transients were characterized for deviations –3% ≤ VOUT ≤ 3% from the nominal output voltage of 1.8 V (±54 mV) and 3.3 V (±99 mV). The upsets typically have duration of 30 μs and peak normalized deviation of 4.3% from the nominal voltage. For more details please refer to Section 9.
  2. A soft-start power re-cycle which results in the VOUT dropping to zero volts and characterized by a long recovery time governed by the soft start (SS) capacitor. This kind of SEFI is referred to here as SSSEFI.
  3. A PGOOD upset ≥ 10% from the nominal output voltage.