SBOS263H October   2002  – December 2024 OPA830

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configurations
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics for D Package VS = ±5V
    6. 6.6  Electrical Characteristics for D Package VS = 5V
    7. 6.7  Electrical Characteristics for D Package VS = 3V
    8. 6.8  Electrical Characteristics for DBV Package VS = ±5V
    9. 6.9  Electrical Characteristics for DBV Package VS = 5V
    10. 6.10 Electrical Characteristics for DBV Package VS = 3V
    11. 6.11 Typical Characteristics: VS = ±5V
    12. 6.12 Typical Characteristics: VS = ±5V, Differential Configuration
    13. 6.13 Typical Characteristics: VS = 5V
    14. 6.14 Typical Characteristics: VS = 5V, Differential Configuration
    15. 6.15 Typical Characteristics: VS = 3V
    16. 6.16 Typical Characteristics: VS = 3V, Differential Configuration
  8. Parameter Measurement Information
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Wideband Voltage-Feedback Operation
      2. 8.1.2  DC Level-Shifting
      3. 8.1.3  Optimizing Resistor Values
      4. 8.1.4  Bandwidth Versus Gain: Noninverting Operation
      5. 8.1.5  Inverting Amplifier Operation
      6. 8.1.6  Output Current and Voltages
      7. 8.1.7  Driving Capacitive Loads
      8. 8.1.8  Distortion Performance
      9. 8.1.9  Noise Performance
      10. 8.1.10 DC Accuracy and Offset Control
      11. 8.1.11 Thermal Analysis
    2. 8.2 Typical Applications
      1. 8.2.1 Single-Supply ADC Interface
      2. 8.2.2 AC-Coupled Output Video Line Driver
      3. 8.2.3 Noninverting Amplifier With Reduced Peaking
      4. 8.2.4 Single-Supply Active Filter
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
        1. 8.3.1.1 Input and ESD Protection
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Demonstration Boards
        2. 9.1.1.2 Macromodel and Applications Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Thermal Analysis

The maximum desired junction temperature sets the maximum allowed internal power dissipation. Do not allow the maximum junction temperature to exceed 150°C.

The operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signal and load; although, for resistive loads connected to mid-supply (VS / 2), PDL is at a maximum when the output is fixed at a voltage equal to VS / 4 or 3VS / 4. Under this condition, PDL = VS2 / c × (16 × RL), where RL includes feedback network loading.

The power in the output stage, and not into the load, determines internal power dissipation.

As a worst-case example, compute the maximum TJ using an OPA830 (SOT-23-5 package) in the circuit of Figure 8-1 operating at the maximum specified ambient temperature of 85°C and driving a 150Ω load at mid-supply.

PD = 10V × 3.9mA + 52 / (16 × (150Ω || 750Ω)) = 51.5mW

Maximum TJ = 85°C + (0.051W × 186.3°C/W) = 94.5°C.

Although this result is still much less than the specified maximum junction temperature, system reliability considerations can require lower specified junction temperatures. The highest possible internal dissipation occurs if the load requires current to be forced into the output at high output voltages, or sourced from the output at low output voltages. This configuration puts a high current through a large internal voltage drop in the output transistors.