SBOS867E August   2017  – August 2025 OPA838

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Related Products
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics VS = 5 V
    6. 6.6 Electrical Characteristics VS = 3 V
    7. 6.7 Typical Characteristics: VS = 5 V
    8. 6.8 Typical Characteristics: VS = 3 V
    9. 6.9 Typical Characteristics: Over Supply Range
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Common-Mode Voltage Range
      2. 7.3.2 Output Voltage Range
      3. 7.3.3 Power-Down Operation
      4. 7.3.4 Trade-Offs in Selecting The Feedback Resistor Value
      5. 7.3.5 Driving Capacitive Loads
    4. 7.4 Device Functional Modes
      1. 7.4.1 Split-Supply Operation (±1.35 V to ±2.7 V)
      2. 7.4.2 Single-Supply Operation (2.7 V to 5.4 V)
      3. 7.4.3 Power Shutdown Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Noninverting Amplifier
      2. 8.1.2 Inverting Amplifier
      3. 8.1.3 Output DC Error Calculations
      4. 8.1.4 Output Noise Calculations
    2. 8.2 Typical Applications
      1. 8.2.1 High-Gain Differential I/O Designs
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Transimpedance Amplifier
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 TINA-TI™ Simulation Software (Free Download)
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Layout Guidelines

Use the OPA838EVM as a reference when designing the circuit board. TI recommends following the EVM layout of the external components near to the amplifier, ground plane construction, and power routing as closely as possible. Follow these general guidelines:

  1. Signal routing must be direct and as short as possible into and out of the op amp.
  2. Use a short and direct feedback path avoiding vias if possible.
  3. Remove ground or power planes from directly under the negative input and output pins of the amplifier.
  4. Place a series output resistor as close to the output pin as possible when driving capacitive or matched loads.
  5. Place a 2.2-µF power-supply decoupling capacitor within two inches of the device and share with other op amps if desired. For split-supply operation, a capacitor is required for both supplies.
  6. Place a 0.1-µF power-supply decoupling capacitor as close to the supply pins as possible, preferably within 0.1 inch. For split-supply operation, a capacitor is required for both supplies.
  7. The PD pin uses logic levels referenced off the negative supply. If the pin is not used, tie the pin to the positive supply to enable the amplifier. If the pin is used, then actively drive the pin. A bypass capacitor is not necessary, but is used for EMI rejection in noisy environments.