SBOSA17A September   2024  – December 2024 TRF1305B1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - TRF1305B1
    6. 6.6 Typical Characteristics - TRF1305B1
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fully Differential RF Amplifier
      2. 7.3.2 Output Common-Mode Control
      3. 7.3.3 Internal Resistor Configuration
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE Pin
        1. 7.4.1.1 Input Common-Mode Extension
      2. 7.4.2 Power-Down Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Interface Considerations
        1. 8.1.1.1 Single-Ended Input
        2. 8.1.1.2 Differential Input
        3. 8.1.1.3 DC Coupling Considerations
      2. 8.1.2 Gain Adjustment With External Resistors in a Differential Input Configuration
    2. 8.2 Typical Application
      1. 8.2.1 TRF1305x1 as ADC Driver in a Zero-IF Receiver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Supply Voltages
      2. 8.3.2 Single-Supply Operation
      3. 8.3.3 Split-Supply Operation
      4. 8.3.4 Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.6 Typical Characteristics - TRF1305B1

at TA = 25℃, VS+ = 5V, VS– = 0V, floating VOCM, PD, and MODE pins, VICM = midsupply, D2D ac-coupled input/output configuration with ZS = 100Ω, ZL = 100Ω, external input resistor network (see Figure 8-3), inputs de-embedded up to RIN_SER and outputs up to the device pins, ambient temperatures shown, and resistor network included as part of DUT characteristic plots (unless otherwise noted)

TRF1305B1 Power Gain (Sdd21) Across Temperature
PIN = –20dBm at each input pin with 50Ω source
Figure 6-1 Power Gain (Sdd21) Across Temperature
TRF1305B1 Input Return Loss (Sdd11) Across Temperature
PIN = –20dBm at each input pin with 50Ω source
Figure 6-3 Input Return Loss (Sdd11) Across Temperature
TRF1305B1 Output Return Loss (Sdd22) Across Temperature
PIN = –20dBm at each input pin with 50Ω source
Figure 6-5 Output Return Loss (Sdd22) Across Temperature
TRF1305B1 OIP3 Across Temperature
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-7 OIP3 Across Temperature
TRF1305B1 OIP3 Across Temperature
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-9 OIP3 Across Temperature
TRF1305B1 IMD3 Lower Across Temperature
At (2f1 – f2) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-11 IMD3 Lower Across Temperature
TRF1305B1 IMD3 Higher Across Temperature
At (2f2 – f1) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-13 IMD3 Higher Across Temperature
TRF1305B1 OIP3 Across VICM and VOCM at 500MHz
PO = 1dBm/tone, 2MHz tone spacing,
dc-coupled inputs with VICM forced through bias tees
Figure 6-15 OIP3 Across VICM and VOCM at 500MHz
TRF1305B1 OIP3 Across VICM and VOCM at 4GHz
PO = 1dBm/tone, 2MHz tone spacing,
dc-coupled inputs with VICM forced through bias tees
Figure 6-17 OIP3 Across VICM and VOCM at 4GHz
TRF1305B1 OIP2 Across Temperature
Per tone PO as shown, 2MHz tone spacing
Figure 6-19 OIP2 Across Temperature
TRF1305B1 IMD2 Across Temperature
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-21 IMD2 Across Temperature
TRF1305B1 HD2 Across Output Power and Temperature
 
Figure 6-23 HD2 Across Output Power and Temperature
TRF1305B1 OP1dB Across Supply Voltage and Temperature
 
Figure 6-25 OP1dB Across Supply Voltage and Temperature
TRF1305B1 Noise Figure Across Temperature
 
Figure 6-27 Noise Figure Across Temperature
TRF1305B1 Step Response
dc-coupled, VS+ = 2.5V, VS– = –2.5V
 
 
Figure 6-29 Step Response
TRF1305B1 S-Parameters Across Temperature in S2D Configuration
S2D, PIN = –20dBm at each input pin with 50Ω source,
de-embedded up to INP and OUTP/OUTM pins
Figure 6-31 S-Parameters Across Temperature in S2D Configuration
TRF1305B1 OIP3 Across Temperature and Output Power
S2D, per tone PO as shown, 2MHz tone spacing,
de-embedded up to INP and OUTP/OUTM pins
Figure 6-33 OIP3 Across Temperature and Output Power
TRF1305B1 HD2 Across Supply Voltage and Output Power
S2D configuration
de-embedded up to INP and OUTP/OUTM pins
Figure 6-35 HD2 Across Supply Voltage and Output Power
TRF1305B1 HD3 Across Supply Voltage and Output Power
S2D configuration
de-embedded up to INP and OUTP/OUTM pins
Figure 6-37 HD3 Across Supply Voltage and Output Power
TRF1305B1 OP1dB Across Supply Voltage and Temperature
S2D, de-embedded up to INP and OUTP/OUTM pins
Figure 6-39 OP1dB Across Supply Voltage and Temperature
TRF1305B1 Noise Figure in S2D Configuration
S2D, de-embedded up to INP and OUTP/OUTM pins
Figure 6-41 Noise Figure in S2D Configuration
TRF1305B1 S2D Step Response
S2D, dc-coupled, VS+ = 2.5V, VS– = –2.5V
 
 
Figure 6-43 S2D Step Response
TRF1305B1 Common-Mode Rejection Ratio (CMRR)
PIN = –20dBm at each driven input pin with 50Ω source,
c in Sdc21 and Scc21 is for common-mode
Figure 6-45 Common-Mode Rejection Ratio (CMRR)
TRF1305B1 Power Gain (Sdd21) Across Supply Voltage
PIN = –20dBm at each input pin with 50Ω source
Figure 6-2 Power Gain (Sdd21) Across Supply Voltage
TRF1305B1 Input Return Loss (Sdd11) Across Supply Voltage
PIN = –20dBm at each input pin with 50Ω source
Figure 6-4 Input Return Loss (Sdd11) Across Supply Voltage
TRF1305B1 Reverse Isolation (Sdd12) Across Temperature
PIN = –20dBm at each input pin with 50Ω source
Figure 6-6 Reverse Isolation (Sdd12) Across Temperature
TRF1305B1 OIP3 Across Supply Voltage
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-8 OIP3 Across Supply Voltage
TRF1305B1 OIP3 Across Supply Voltage
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-10 OIP3 Across Supply Voltage
TRF1305B1 IMD3 Lower Across Supply Voltage
At (2f1 – f2) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-12 IMD3 Lower Across Supply Voltage
TRF1305B1 IMD3 Higher Across Supply Voltage
At (2f2 – f1) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-14 IMD3 Higher Across Supply Voltage
TRF1305B1 OIP3 Across VICM and VOCM at 2GHz
PO = 1dBm/tone, 2MHz tone spacing,
dc-coupled inputs with VICM forced through bias tees
Figure 6-16 OIP3 Across VICM and VOCM at 2GHz
TRF1305B1 OIP3 Across VICM and VOCM at 5GHz
PO = 1dBm/tone, 2MHz tone spacing,
dc-coupled inputs with VICM forced through bias tees
Figure 6-18 OIP3 Across VICM and VOCM at 5GHz
TRF1305B1 OIP2 Across Supply Voltage
Per tone PO as shown, 2MHz tone spacing
Figure 6-20 OIP2 Across Supply Voltage
TRF1305B1 IMD2 Across Temperature
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-22 IMD2 Across Temperature
TRF1305B1 HD3 Across Output Power and Temperature
 
Figure 6-24 HD3 Across Output Power and Temperature
TRF1305B1 Differential Input vs Differential Output Power
 
Figure 6-26 Differential Input vs Differential Output Power
TRF1305B1 Noise Figure at Each Single-Ended Output
Differential input, single-ended output
Figure 6-28 Noise Figure at Each Single-Ended Output
TRF1305B1 Overdrive Recovery Response
dc-coupled, VS+ = 2.5V, VS– = –2.5V, 2x to 5x output voltages
are with an input voltage 2 to 5 times of VINP and VINM
as shown, respectively
Figure 6-30 Overdrive Recovery Response
TRF1305B1 S-Parameters Across Temperature in S2D Configuration
S2D, PIN = –20dBm at each input pin with 50Ω source,
de-embedded up to INP and OUTP/OUTM pins
Figure 6-32 S-Parameters Across Temperature in S2D Configuration
TRF1305B1 OIP2 Across Temperature and Output Power
S2D, per tone PO as shown, 2MHz tone spacing,
de-embedded up to INP and OUTP/OUTM pins
Figure 6-34 OIP2 Across Temperature and Output Power
TRF1305B1 HD2 Across Temperature and Output Power
S2D configuration
de-embedded up to INP and OUTP/OUTM pins
Figure 6-36 HD2 Across Temperature and Output Power
TRF1305B1 HD3 Across Temperature and Output Power
S2D configuration
de-embedded up to INP and OUTP/OUTM pins
Figure 6-38 HD3 Across Temperature and Output Power
TRF1305B1 Single-Ended Input vs Differential Output Power
S2D, de-embedded up to INP and OUTP/OUTM pins
Figure 6-40 Single-Ended Input vs Differential Output Power
TRF1305B1 Power Up and Power Down Timing
S2D, dc-coupled, VS+ = 2.5V, VS– = –2.5V
Figure 6-42 Power Up and Power Down Timing
TRF1305B1 S2D Overdrive Recovery Response
S2D, dc-coupled, VS+ = 2.5V, VS– = –2.5V,
2x to 5x output voltages are with an input voltage 2 to 5 times
that of VINP as shown, respectively
Figure 6-44 S2D Overdrive Recovery Response
TRF1305B1 Amplitude and Phase Imbalance
S2D, PIN = –20dBm at each input pin with 50Ω source
 
Figure 6-46 Amplitude and Phase Imbalance