SBOSA42B June   2024  – December 2025 OPA2596 , OPA596

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information OPA596
    5. 5.5 Thermal Information OPA596
    6. 5.6 Electrical Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 MUX-Friendly Inputs
      2. 6.3.2 Thermal Protection
      3. 6.3.3 Advanced Slew Boost
      4. 6.3.4 Overload Recovery
      5. 6.3.5 Full-Power Bandwidth Improved
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Bridge-Connected Piezoelectric Driver
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 DAC Output Gain and Buffer
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
      3. 7.2.3 Single-Supply Piezoelectric Driver
      4. 7.2.4 High-Side Current Sense
      5. 7.2.5 High-Voltage Instrumentation Amplifier
      6. 7.2.6 Composite Amplifier
    3. 7.3 Creepage and Clearance
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 Thermal Considerations
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.6 Electrical Characteristics

at VS = 85V (±42.5V), TA = 25°C, RL = 10kΩ to mid-supply, and VCM = VOUT = mid-supply (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage ±0.2 ±1 mV
dVOS/dT Input offset voltage drift TA = –40°C to +125°C(1) ±1 ±6 µV/°C
PSRR Power supply rejection ratio 8V ≤ VS ≤ 85V ±1 ±5 µV/V
INPUT BIAS CURRENT
IB Input bias current(1) ±5 ±15 pA
TA = –40°C to +85°C ±50
TA = –40°C to +125°C ±1 nA
IOS Input offset current(1) ±5 ±15 pA
TA = –40°C to +85°C ±50
TA = –40°C to +125°C ±1 nA
NOISE
Input voltage noise f = 0.1Hz to 10Hz 1.4 µVPP
en Input voltage noise density f = 100Hz 17.8 nV/√Hz
f = 1kHz 12.9
f = 10kHz 12.8
in Current noise density f = 1kHz 7 fA/√Hz
INPUT VOLTAGE
VCM Common-mode voltage Linear operation (V–) – 0.1 (V+) – 3.5 V
CMRR Common-mode rejection (V–) ≤ VCM ≤ (V+) – 3.5V 120 140 dB
TA = –40°C to +125°C(1) 120 140
INPUT IMPEDANCE
Differential 100 || 2.5 MΩ || pF
Common-mode 10 || 5.5 GΩ || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain (V–) + 1V < VO < (V+) – 1.5V,
RL = 10kΩ to mid-supply(1)		 134 140 dB
TA = –40°C to +125°C 120 140
(V–) + 3V < VO < (V+) – 3.5V,
RL = 2kΩ to mid-supply		 116 126
OPA596
TA = –40°C to +125°C(1)		 116 126
OPA2596
TA = –40°C to +125°C(1)		 97 110
FREQUENCY RESPONSE
GBW Gain-bandwidth product G = 1 2.25 MHz
G = 10 3
G = 100 3.75
SR Slew rate G = ±1, VO = 70V step 100 V/µs
tS Settling time To ±0.01%, G = 1, VO = 70V step, CL = 20pF 3 µs
Overload recovery G = –10 115 ns
THD+N Total harmonic distortion + noise G = +1, VO = 70VPP, f = 1kHz RL = 10kΩ –102 dB
RL = 2kΩ –95
OUTPUT
VO Voltage output swing from rail(1) No load  40 50 mV
RL = 10kΩ to mid-supply  420 500
RL = 2kΩ to mid-supply  2 2.5 V
ISC Output current ±30 mA
CLOAD Capacitive load drive 1 nF
ZO Open-loop output impedance f = 1MHz 550 Ω
POWER SUPPLY
IQ Quiescent current IO = 0mA 420 490 µA
TA = –40°C to +125°C(1) 500
TEMPERATURE
Overtemperature shutdown Shutdown temperature, TJ 170 °C
Thermal hysteresis 20
(1) Specification established from device population bench system measurements across multiple lots.