SBOSAE8C October   2023  – April 2025 OPA2323 , OPA323 , OPA4323

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information for Single Channel
    5. 6.5 Thermal Information for Dual Channel
    6. 6.6 Thermal Information for Quad Channel
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Operating Voltage
      2. 7.3.2  Rail-to-Rail Input
      3. 7.3.3  Rail-to-Rail Output
      4. 7.3.4  Common-Mode Rejection Ratio (CMRR)
      5. 7.3.5  Capacitive Load and Stability
      6. 7.3.6  Overload Recovery
      7. 7.3.7  EMI Rejection
      8. 7.3.8  ESD and Electrical Overstress
      9. 7.3.9  Input ESD Protection
      10. 7.3.10 Shutdown Function
      11. 7.3.11 Packages with an Exposed Thermal Pad
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 OPAx323 in Low-Side, Current Sensing Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4.     Trademarks
    5. 9.4 Electrostatic Discharge Caution
    6. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

OPA4323 OPA323 OPA2323 OPA323 DBV Package,5-Pin SOT-23(Top View)Figure 5-1 OPA323 DBV Package,
5-Pin SOT-23
(Top View)
OPA4323 OPA323 OPA2323 OPA323 DCK and DRL Package,5-Pin SC70 and 5-Pin SOT-5X3(Top View)Figure 5-2 OPA323 DCK and DRL Package,
5-Pin SC70 and 5-Pin SOT-5X3
(Top View)
Table 5-1 Pin Functions: OPA323
PIN TYPE(1) DESCRIPTION
NAME SOT-23 SC70, SOT-5X3
IN– 4 3 I Inverting input
IN+ 3 1 I Noninverting input
OUT 1 4 O Output
V– 2 2 I Negative (low) supply or ground (for single-supply operation)
V+ 5 5 I Positive (high) supply
(1) I = input, O = output
OPA4323 OPA323 OPA2323 OPA323S DBV Package,6-Pin SOT-23(Top View)Figure 5-3 OPA323S DBV Package,
6-Pin SOT-23
(Top View)
OPA4323 OPA323 OPA2323 OPA323S DCK Package,6-Pin SC70(Top View)Figure 5-4 OPA323S DCK Package,
6-Pin SC70
(Top View)
Table 5-2 Pin Functions: OPA323S
PINTYPE(1)DESCRIPTION
NAMESOT-23SC70
IN–43IInverting input
IN+31INoninverting input
OUT14OOutput
SHDN55IShutdown: low = amp disabled, high = amp enabled
See Shutdown Function for more information
V–22INegative (low) supply or ground (for single-supply operation)
V+66IPositive (high) supply
(1) I = input, O = output
OPA4323 OPA323 OPA2323 OPA2323 D, PW, DGK, and DDF Package, SOIC, TSSOP, VSSOP, and SOT-23-THIN(Top View)Figure 5-5 OPA2323 D, PW, DGK, and DDF Package,
SOIC, TSSOP, VSSOP, and SOT-23-THIN
(Top View)
OPA4323 OPA323 OPA2323 OPA2323 DSG Package,8-Pin WSON with Exposed Thermal Pad(Top View)
Connect exposed thermal pad to V–. For more information, see Packages with an Exposed Thermal Pad.
Figure 5-6 OPA2323 DSG Package,
8-Pin WSON with Exposed Thermal Pad
(Top View)
Table 5-3 Pin Functions: OPA2323
PINTYPE(1)DESCRIPTION
NAMESOIC, TSSOP, VSSOP, SOT-23-THIN, WSON
IN1–2IInverting input, channel 1
IN1+3INoninverting input, channel 1
IN2–6IInverting input, channel 2
IN2+5INoninverting input, channel 2
OUT11OOutput, channel 1
OUT27OOutput, channel 2
V–4INegative (low) supply or ground (for single-supply operation)
V+8IPositive (high) supply
(1) I = input, O = output
OPA4323 OPA323 OPA2323 OPA2323S RUG Package10-Pin X2QFN(Top View)Figure 5-7 OPA2323S RUG Package
10-Pin X2QFN
(Top View)
Table 5-4 Pin Functions: OPA2323S
PIN TYPE(1) DESCRIPTION
NAME X2QFN
IN1– 9 I Inverting input, channel 1
IN1+ 10 I Noninverting input, channel 1
IN2– 5 I Inverting input, channel 2
IN2+ 4 I Noninverting input, channel 2
OUT1 8 O Output, channel 1
OUT2 6 O Output, channel 2
SHDN1 2 I Shutdown: low = amp disabled, high = amp enabled, channel 1.
For more information, see Shutdown Function.
SHDN2 3 I Shutdown: low = amp disabled, high = amp enabled, channel 2
For more information, see Shutdown Function.
V– 1 I Negative (low) supply or ground (for single-supply operation)
V+ 7 I Positive (high) supply
(1) I = input, O = output
OPA4323 OPA323 OPA2323 OPA4323 D, PW and DYY Package,14-Pin SOIC, TSSOP, SOT-23-THN(Top View)Figure 5-8 OPA4323 D, PW and DYY Package,
14-Pin SOIC, TSSOP, SOT-23-THN
(Top View)
Table 5-5 Pin Functions: OPA4323
PIN TYPE(1) DESCRIPTION
NAME SOIC, TSSOP
IN1– 2 I Inverting input, channel 1
IN1+ 3 I Noninverting input, channel 1
IN2– 6 I Inverting input, channel 2
IN2+ 5 I Noninverting input, channel 2
IN3– 9 I Inverting input, channel 3
IN3+ 10 I Noninverting input, channel 3
IN4– 13 I Inverting input, channel 4
IN4+ 12 I Noninverting input, channel 4
OUT1 1 O Output, channel 1
OUT2 7 O Output, channel 2
OUT3 8 O Output, channel 3
OUT4 14 O Output, channel 4
V– 11 I Negative (low) supply or ground (for single-supply operation)
V+ 4 I Positive (high) supply
(1) I = input, O = output
OPA4323 OPA323 OPA2323 OPA4323S RTE Package,16-Pin WQFN With Exposed Thermal Pad(Top View)
A. Connect thermal pad to V–.
Figure 5-9 OPA4323S RTE Package,
16-Pin WQFN With Exposed Thermal Pad
(Top View)
Table 5-6 Pin Functions: OPA4323S
PIN TYPE(1) DESCRIPTION
NAME WQFN
IN1+ 1 I Noninverting input, channel 1
IN1– 16 I Inverting input, channel 1
IN2+ 3 I Noninverting input, channel 2
IN2– 4 I Inverting input, channel 2
IN3+ 10 I Noninverting input, channel 3
IN3– 9 I Inverting input, channel 3
IN4+ 12 I Noninverting input, channel 4
IN4– 13 I Inverting input, channel 4
SHDN12 6 I Shutdown: low = amp disabled, high = amp enabled, channel 1 and 2.
For more information, see Shutdown Function.
SHDN34 7 I Shutdown: low = amp disabled, high = amp enabled, channel 3 and 4.
For more information, see Shutdown Function.
OUT1 15 O Output, channel 1
OUT2 5 O Output, channel 2
OUT3 8 O Output, channel 3
OUT4 14 O Output, channel 4
V– 11 I Negative (low) supply or ground (for single-supply operation)
V+ 2 I Positive (high) supply
(1) I = input, O = output