SBVS470 February   2026 TPS7N59

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Voltage Setting and Regulation
      2. 6.3.2 Low-Noise, Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 6.3.3 Programmable Soft-Start
      4. 6.3.4 Precision Enable and UVLO
      5. 6.3.5 Power-Good Pin (PG Pin)
      6. 6.3.6 Active Discharge
      7. 6.3.7 Thermal Shutdown Protection (TSD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
      4. 6.4.4 Current-Limit Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1  Precision Enable (External UVLO)
      2. 7.1.2  Undervoltage Lockout (UVLO) Operation
        1. 7.1.2.1 IN Pin UVLO
        2. 7.1.2.2 BIAS UVLO
        3. 7.1.2.3 Typical UVLO Operation
      3. 7.1.3  Dropout Voltage (VDO)
      4. 7.1.4  Input and Output Capacitor Requirements (CIN and COUT)
      5. 7.1.5  Recommended Capacitor Types
      6. 7.1.6  Soft-Start, Noise Reduction (NR/SS Pin), and Power-Good (PG Pin)
      7. 7.1.7  Optimizing Noise and PSRR
      8. 7.1.8  Adjustable Operation
      9. 7.1.9  Load Transient Response
      10. 7.1.10 Sequencing
      11. 7.1.11 Power-Good Functionality
      12. 7.1.12 Current Mode Margining
      13. 7.1.13 Voltage Mode Margining
      14. 7.1.14 Power Dissipation (PD)
      15. 7.1.15 Estimating Junction Temperature
      16. 7.1.16 TPS7N58EVM-184 Thermal Analysis
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

6.1 Overview

The TPS7N59 is a low-noise (2.5μVRMS over 10Hz to 100kHz bandwidth),high-accuracy (1%), ultra-low-dropout (LDO) linear voltage regulator with an input range of 0.7V to 6.0V and an output voltage range from 0.5V to 5.2V. This device uses remarkable circuitry to achieve wide bandwidth and high loop gain, resulting in ultra-high PSRR even with very low operational headroom [VOpHr = (VIN – VOUT)]. At a high level, the device has two main primary features (the current reference and the unity-gain LDO buffer) and a few secondary features (such as the adjustable soft-start inrush control, precision enable and PG pin).

The current reference is controlled by the REF pin. This pin sets the output voltage with a single resistor, the pin sets the start-up time and filters the noise generated by the reference and external RREF

The unity-gain configuration sets the output voltage. The low noise does not increase with output voltage and provides wideband PSRR. As such, the SNS pin is only used for remote sensing of the load.

The low-noise current reference, 50μA typical, is used in conjunction with an external resistor (RREF) to set the output voltage. This process allows the output voltage range to be set from 0.5V to 5.2V. To achieve low noise and allow for a soft-start inrush, an external capacitor, CREF (typically 4.7μF), is placed in parallel with the RREF resistor attenuating the band-gap noise. The RREF resistor sets the output voltage. This unity-gain LDO provides ultra-high PSRR over a wide frequency range without compromising load and line transients.

The EN pin sets the precision enable feature; a resistor divider on this pin selects the optimal input voltage at which the device starts. There are three independent undervoltage lockout (UVLO) voltages in this device: the internal fixed UVLO thresholds for the IN and BIAS rails, and the externally adjustable UVLO threshold using the EN pin.

This regulator offers current limit, thermal protection, is fully specified from –40°C to +125°C, and is offered in a 24-pin WQFN, 4mm × 4mm thermally efficient package.