SBVU073A november 2021 – june 2023 TPS7A14
3 Board Layout
Figure 3-1 through Figure 3-6 illustrate the board layout for the TPS7A14EVM-058 PCB.
Figure 3-7 through Figure 3-12 illustrate the board layout for the TPS7A14EVM-095 PCB
The TPS7A14EVM-058 and TPS7A14EVM-095 dissipate power, which can cause some components to experience an increase in temperature. The TPS7A14 LDO, LMG1020YFFR gate driver, and pulsed resistors R2, R3, R4, R5, and R6 are most at risk of raising to a high junction temperature during normal operation.
Figure 3-1 TPS7A14EVM-058 Top
Assembly Layer and Silk Screen
Figure 3-3 TPS7A14EVM-058 Layer
2
Figure 3-5 TPS7A14EVM-058 Bottom
Layer Routing
Figure 3-2 TPS7A14EVM-058 Top Layer
Routing
Figure 3-4 TPS7A14EVM-058 Layer
3
Figure 3-6 TPS7A14EVM-058 Bottom
Assembly Layer and Silk Screen
Figure 3-7 TPS7A14EVM-095 Top Assembly Layer and Silk Screen
Figure 3-9 TPS7A14EVM-095 Layer 2
Figure 3-11 TPS7A14EVM-095 Bottom Layer Routing
Figure 3-8 TPS7A14EVM-095 Top Layer Routing
Figure 3-10 TPS7A14EVM-095 Layer 3
Figure 3-12 TPS7A14EVM-095 Bottom Assembly Layer and Silk Screen