SCASE17A September   2024  – June 2025 SN74AC2G101

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 CMOS Schmitt-Trigger Inputs
      3. 7.3.3 Latching Logic
      4. 7.3.4 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Reference
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.7 Switching Characteristics

over operating free-air temperature range; CL = 50pF typical values measured at TA = 25°C (unless otherwise noted). See Parameter Measurement Information
PARAMETER FROM (INPUT) TO (OUTPUT) VCC -40°C to 125°C UNIT
MIN TYP MAX
tpd CLKA Q 1.5V 50.2 ns
3.3V ± 0.3V 16.4 ns
5V ± 0.5V 11.3 ns
6V 9.1 ns
CLKB Q 1.5V 50.1 ns
3.3V ± 0.3V 16.4 ns
5V ± 0.5V 11.2 ns
6V 9.2 ns
CLKC Q 1.5V 50.3 ns
3.3V ± 0.3V 15 ns
5V ± 0.5V 10.4 ns
6V 8.7 ns
CLKD Q 1.5V 45.9 ns
3.3V ± 0.3V 15.3 ns
5V ± 0.5V 10.5 ns
6V 8.5 ns
CLR Q 1.5V 36.1 ns
3.3V ± 0.3V 13.1 ns
5V ± 0.5V 9.7 ns
6V 8.2 ns
tsk(o) Q 1.5V 4 ns
6V 1 ns
CPD(1) CLK or CLK INH QH 5V 50 pF
(1) Power dissipation capacitance measured with CL = 50pF, F = 1MHz