SCASE49
January 2025
SN74LV8T374-EP
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Switching Characteristics
5.7
Timing Characteristics
5.8
Typical Characteristics
6
Parameter Measurement Information
7
Pin Configuration and Functions
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Balanced CMOS 3-State Outputs
8.3.2
LVxT Enhanced Input Voltage
8.3.2.1
Up Translation
8.3.2.2
Down Translation
8.3.3
Clamp Diode Structure
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.1.1
Power Considerations
9.2.1.2
Input Considerations
9.2.1.3
Output Considerations
9.2.2
Detailed Design Procedure
9.2.3
Application Curve
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
Receiving Notification of Documentation Updates
10.3
Support Resources
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
1
Features
Wide operating range of 1.65V to 5.5V
5.5V tolerant input pins
Single-supply voltage translator (refer to
LVxT Enhanced Input Voltage
):
Up translation:
1.2V to 1.8V
1.5V to 2.5V
1.8V to 3.3V
3.3V to 5.0V
Down translation:
5.0V, 3.3V, 2.5V to 1.8V
5.0V, 3.3V to 2.5V
5.0V to 3.3V
Up to 150Mbps with 5V or 3.3V V
CC
Supports standard function pinout
Latch-up performance exceeds 250mA
per JESD 17
Supports defense and aerospace applications:
Controlled baseline
One assembly and test site
One fabrication site
Extended product life cycle
Product traceability