SCASE58 January   2025 SN74LV8T595-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS 3-State Outputs
      2. 7.3.2 LVxT Enhanced Input Voltage
        1. 7.3.2.1 Up Translation
        2. 7.3.2.2 Down Translation
      3. 7.3.3 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.7 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER DESCRIPTION CONDITION VCC TA = 25°C -55°C to 125°C UNIT
MIN MAX MIN MAX
fCLOCK Clock frequency 1.8V 13.5 11.4 MHz
tW Pulse duration RCLK or SRCLK high or low 1.8V 16 18 ns
tW Pulse duration SCRCLR low 1.8V 12 13 ns
tSU Setup time SER before SRCLK↑ 1.8V 10 12 ns
tSU Setup time SRCLK↑ before RCLK↑ 1.8V 29 51 ns
tSU Setup time SRCLR low before RCLK↑ 1.8V 35 54 ns
tSU Setup time SRCLR high (inactive) before SRCLK↑ 1.8V 8 10 ns
tH Hold time SER after SRCLK↑ 1.8V 1 1 ns
fCLOCK Clock frequency 2.5V 29 22 MHz
tW Pulse duration RCLK or SRCLK high or low 2.5V 11 13 ns
tW Pulse duration SCRCLR low 2.5V 9 10 ns
tSU Setup time SER before SRCLK↑ 2.5V 8 9 ns
tSU Setup time SRCLK↑ before RCLK↑ 2.5V 17 30 ns
tSU Setup time SRCLR low before RCLK↑ 2.5V 20 33 ns
tSU Setup time SRCLR high (inactive) before SRCLK↑ 2.5V 6 7 ns
tH Hold time SER after SRCLK↑ 2.5V 1 1 ns
fCLOCK Clock frequency 3.3V 46 32 MHz
tW Pulse duration RCLK or SRCLK high or low 3.3V 11 12 ns
tW Pulse duration SCRCLR low 3.3V 9 10 ns
tSU Setup time SER before SRCLK↑ 3.3V 8 9 ns
tSU Setup time SRCLK↑ before RCLK↑ 3.3V 13 21 ns
tSU Setup time SRCLR low before RCLK↑ 3.3V 17 24 ns
tSU Setup time SRCLR high (inactive) before SRCLK↑ 3.3V 6 7 ns
tH Hold time SER after SRCLK↑ 3.3V 1 1 ns
fCLOCK Clock frequency 5V 64 1 MHz
tW Pulse duration RCLK or SRCLK high or low 5V 11 12 ns
tW Pulse duration SCRCLR low 5V 9 10 ns
tSU Setup time SER before SRCLK↑ 5V 7 8 ns
tSU Setup time SRCLK↑ before RCLK↑ 5V 11 17 ns
tSU Setup time SRCLR low before RCLK↑ 5V 12 18 ns
tSU Setup time SRCLR high (inactive) before SRCLK↑ 5V 6 7 ns
tH Hold time SER after SRCLK↑ 5V 1 1 ns