SCASE60 January   2025 SN74LV8T164-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 LVxT Enhanced Input Voltage
        1. 7.3.2.1 Up Translation
        2. 7.3.2.2 Down Translation
      3. 7.3.3 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Application Information
      2. 8.1.2 Design Requirements
        1. 8.1.2.1 Power Considerations
        2. 8.1.2.2 Input Considerations
        3. 8.1.2.3 Output Considerations
      3. 8.1.3 Detailed Design Procedure
      4. 8.1.4 Application Curves
    2. 8.2 Power Supply Recommendations
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.7 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER DESCRIPTION CONDITION VCC TA = 25°C -55°C to 125°C UNIT
MIN MAX MIN MAX
fCLOCK Clock frequency 1.8V 25.5 22.5 MHz
tW Pulse duration CLR low 1.8V 12 12.5 ns
tW Pulse duration CLK high or low 1.8V 12.5 14.5 ns
tSU Setup time Data before CLK↑ 1.8V 10 12.5 ns
tSU Setup time CLR inactive 1.8V 7.5 9.5 ns
tH Hold time Data after CLK↑ 1.8V 1 1 ns
fCLOCK Clock frequency 2.5V 49 40 MHz
tW Pulse duration CLR low 2.5V 9 10 ns
tW Pulse duration CLK high or low 2.5V 9 10 ns
tSU Setup time Data before CLK↑ 2.5V 8 9.5 ns
tSU Setup time CLR inactive 2.5V 5.5 6.5 ns
tH Hold time Data after CLK↑ 2.5V 1 1 ns
fCLOCK Clock frequency 3.3V 59 55 MHz
tW Pulse duration CLR low 3.3V 8.5 9 ns
tW Pulse duration CLK high or low 3.3V 8.5 9 ns
tSU Setup time Data before CLK↑ 3.3V 7.5 8 ns
tSU Setup time CLR inactive 3.3V 5 5.5 ns
tH Hold time Data after CLK↑ 3.3V 1 1 ns
fCLOCK Clock frequency 5V 75 75 62.5 MHz
tW Pulse duration CLR low 5V 8.5 8.5 ns
tW Pulse duration CLK high or low 5V 8 8.5 ns
tSU Setup time Data before CLK↑ 5V 6 6.5 ns
tSU Setup time CLR inactive 5V 4.5 5 ns
tH Hold time Data after CLK↑ 5V 1 1 ns