SCASE60A January   2025  – May 2026 SN74LV8T164-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 LVxT Enhanced Input Voltage
        1. 7.3.2.1 Up Translation
        2. 7.3.2.2 Down Translation
      3. 7.3.3 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Typical Application
    2. 8.2 Application Information
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.2.1 Up Translation

Input signals can be up translated using the SN74LV8T164-EP. The voltage applied at VCC determines the output voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical Characteristics tables. When connected to a high-impedance input, the output voltage is approximately VCC in the HIGH state, and 0V in the LOW state.

The inputs have reduced thresholds that allow for input HIGH state levels, which are much lower than standard values. For example, standard CMOS inputs for a device operating at a 5V supply has a VIH(MIN) of 3.5V. For the SN74LV8T164-EP, VIH(MIN) with a 5V supply is only 2V, which would allow for up-translation from a typical 2.5V to 5V signals.

Verify that the input signals in the HIGH state are above VIH(MIN) and input signals in the LOW state are lower than VIL(MAX) as shown in Figure 7-2.

Up Translation Combinations are as follows:

  • 1.8V VCC – Inputs from 1.2V
  • 2.5V VCC – Inputs from 1.8V
  • 3.3V VCC – Inputs from 1.8V and 2.5V
  • 5.0V VCC – Inputs from 2.5V and 3.3V

SN74LV8T164-EP LVxT Up and Down Translation Example Figure 7-2 LVxT Up and Down Translation Example