SCASE71 January   2025 SN54SC8T165-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 SCxT Enhanced Input Voltage
        1. 7.3.2.1 Up Translation
        2. 7.3.2.2 Down Translation
      3. 7.3.3 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.7 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER DESCRIPTION CONDITION VCC TA = 25°C -55°C to 125°C UNIT
MIN MAX MIN MAX
tW Pulse duration SH/LD low 1.2 V ± 0.1 V 6.1 6.9 ns
tW Pulse duration CLK high or low 1.2V ± 0.1V 41.3 7 ns
tSU Setup time SH/LD high before CLK↑ 1.2V ± 0.1V 50.8 8 ns
tSU Setup time SER before CLK↑ 1.2V ± 0.1V 34.6 10.1 ns
tSU Setup time CLK INH low before CLK↑ 1.2V ± 0.1V 1 1 ns
tSU Setup time CLK INH high before CLK↑ 1.2V ± 0.1V 1 1 ns
tSU Setup time Data before SH/LD↓ 1.2V ± 0.1V 49.4 10 ns
tH Hold time SER data after CLK↑ 1.2V ± 0.1V 6.43 0 ns
tH Hold time PAR data after SH/LD↓ 1.2V ± 0.1V 7.61 0 ns
tW Pulse duration SH/LD low 1.8V ± 0.15V 6.1 6.9 ns
tW Pulse duration CLK high or low 1.8V ± 0.15V 12.3 7 ns
tSU Setup time SH/LD high before CLK↑ 1.8V ± 0.15V 9.03 8 ns
tSU Setup time SER before CLK↑ 1.8V ± 0.15V 8.83 10.1 ns
tSU Setup time CLK INH low before CLK↑ 1.8V ± 0.15V 1 1 ns
tSU Setup time CLK INH high before CLK↑ 1.8V ± 0.15V 1 1 ns
tSU Setup time Data before SH/LD↓ 1.8V ± 0.15V 15.7 10 ns
tH Hold time SER data after CLK↑ 1.8V ± 0.15V 2.2 0 ns
tH Hold time PAR data after SH/LD↓ 1.8V ± 0.15V 2.06 0 ns
tW Pulse duration SH/LD low 2.5V ± 0.2V 4.3 5.4 ns
tW Pulse duration CLK high or low 2.5V ± 0.2V 8.63 4.5 ns
tSU Setup time SH/LD high before CLK↑ 2.5V ± 0.2V 6.93 4.5 ns
tSU Setup time SER before CLK↑ 2.5V ± 0.2V 7.2 5.9 ns
tSU Setup time CLK INH low before CLK↑ 2.5V ± 0.2V 1 1 ns
tSU Setup time CLK INH high before CLK↑ 2.5V ± 0.2V 1 1 ns
tSU Setup time Data before SH/LD↓ 2.5V ± 0.2V 11.1 6.9 ns
tH Hold time SER data after CLK↑ 2.5V ± 0.2V 1.32 0 ns
tH Hold time PAR data after SH/LD↓ 2.5V ± 0.2V 1 0 ns
tW Pulse duration SH/LD low 3.3V ± 0.3V 4.3 4.3 ns
tW Pulse duration CLK high or low 3.3V ± 0.3V 8.13 4.3 ns
tSU Setup time SH/LD high before CLK↑ 3.3V ± 0.3V 6.24 2.9 ns
tSU Setup time SER before CLK↑ 3.3V ± 0.3V 6.67 4 ns
tSU Setup time CLK INH low before CLK↑ 3.3V ± 0.3V 1 1 ns
tSU Setup time CLK INH high before CLK↑ 3.3V ± 0.3V 1 1 ns
tSU Setup time Data before SH/LD↓ 3.3V ± 0.3V 9.86 5.3 ns
tH Hold time SER data after CLK↑ 3.3V ± 0.3V 1 0 ns
tH Hold time PAR data after SH/LD↓ 3.3V ± 0.3V 1 0 ns