SCASE75A December   2024  – June 2025 SN74AC165-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7.     13
    8. 5.7 Switching Characteristics
    9. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 Latching Logic
      3. 7.3.3 Standard CMOS Inputs
      4. 7.3.4 Wettable Flanks
      5. 7.3.5 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

SN74AC165-Q1 PW Package,16-Pin TSSOP(Top View)Figure 4-1 PW Package,
16-Pin TSSOP
(Top View)
SN74AC165-Q1 BQB Package,16-Pin WQFN(Transparent Top View)Figure 4-2 BQB Package,
16-Pin WQFN
(Transparent Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
SH/LD 1 I Shift or load mode select
CLK 2 I Shift register clock
E 3 I E register data
F 4 I F register data
G 5 I G register data
H 6 I H register data
QH 7 O Inverted shift register output
GND 8 G Ground
QH 9 O Shift register output
SER 10 I Serial data input
A 11 I A register data
B 12 I B register data
C 13 I C register data
D 14 I D register data
CLK INH 15 I Clock inhibit
VCC 16 P Positive supply
Thermal pad(2) — The thermal pad can be connected to GND or left floating. Do not connect to any other signal or supply.
(1) I = input, O = output, P = power, G = ground
(2) For BQB package only