SCDS038N December   1997  – July 2026 SN74CBTLV3126

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - D, DGV, DBQ, PW, RGY
    6. 5.6 Electrical Characteristics - DYY and BQA
    7. 5.7 Switching Characteristics - D, DGV, DBQ, PW, RGY
    8. 5.8 Switching Characteristics - DYY and BQA
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Function Table (Each Bus Switch)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Protocol and Signal Isolation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

3 Description

The SN74CBTLV3126 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE) input is low.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature verifies that damaging current does not backflow through the device when powered down. The SN74CBTLV3126 device has isolation during power off.

To verify the high-impedance state during power up or power down, tie OE to GND through a pull down resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Package Information
PART NUMBERPACKAGE(1)PACKAGE SIZE(2)
SN74CBTLV3126SOIC (D, 14)8.65mm × 3.91mm
TVSOP (DGV, 14)3.60mm × 4.40mm
TSSOP (PW, 14)5.00mm × 4.40mm
VQFN (RGY, 14)4.00mm × 3.50mm
SSOP (DBQ, 16)4.90mm × 3.90mm
SOT (DYY,14)4.20mm × 2.00mm
WQFN (BQA,14)3.00mm × 2.50mm
(1) For all available packages, see the package option addendum at the end of the data sheet.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
SN74CBTLV3126 Simplified Schematic, Each FET SwitchSimplified Schematic, Each FET Switch