SCDS040N December   1997  – July 2026 SN74CBTLV3257

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Thermal Information
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Electrical Characteristics - DBQ, DGV, D, PW and RGY only
    6. 5.6 Electrical Characteristics - DYY and BQB Package only
    7. 5.7 Switching Characteristics - DBQ, DGV, D, PW and RGY only
    8. 5.8 Switching Characteristics - DYY and BQB Package only
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

3 Description

The SN74CBTLV3257 device is a 1-of-8 high-speed FET multiplexer/demultiplexer. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The select inputs (S0, S1, S2) control the data flow. The FET multiplexers/demultiplexers are disabled when the output-enable ( OE) input is high. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current cannot backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Package Information
PART NUMBERPACKAGE (1)PACKAGE SIZE(2)
SN74CBTLV3257DBQRDBQ (SSOP, 16)4.90mm × 3.90mm
SN74CBTLV3257PWRPW (TSSOP, 16)5.00mm × 4.40mm
SN74CBTLV3257DGVRDGV(TVSOP,16)3.60mm × 4.40mm
SN74CBTLV3257DRD (SOIC, 16)9.90mm × 3.91mm
SN74CBTLV3257RGYRRGY (VQFN, 16)4.00mm × 3.50mm
SN74CBTLV3257DYYSOT (16)4.20mm × 2.00mm
SN74CBTLV3257BQBWQFN (16)3.50mm × 2.50mm
(1) For more information, see Section 11.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
SN74CBTLV3257 Simplified Schematic (Each FET Switch)Simplified Schematic (Each FET Switch)