SCDS154C October   2003  – August 2026 SN74CB3Q3244

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Description
  4. 3Pin Configuration and Functions
  5. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Switching Characteristics
    7. 4.7 Typical Characteristics
  6. 5Parameter Measurement Information
  7. 6Device and Documentation Support
    1. 6.1 Receiving Notification of Documentation Updates
    2. 6.2 Support Resources
    3. 6.3 Trademarks
    4. 6.4 Electrostatic Discharge Caution
    5. 6.5 Glossary
  8. 7Revision History
  9. 8Mechanical, Packaging, and Orderable Information

Description

The SN74CB3Q3244 is a high-bandwidth FET bus switch using a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3244 provides an optimized interface design for broadband communications, networking, and data-intensive computing systems.

The SN74CB3Q3244 is organized as two 4-bit bus switches with separate output-enable (1 OE, 2 OE) inputs. The device can be used as two 4-bit bus switches or as one 8-bit bus switch. When OE is low, the associated 4-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 4-bit bus switch is OFF, and the high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when powered down. The device has isolation during power off.

To make sure of the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
SN74CB3Q3244 DBQ (SSOP, 20) 8.65mm × 6mm
DGV (TVSOP, 20) 5mm × 6.4mm
RGY (VQFN, 20) 4.5mm × 3.5mm
PW (TSSOP, 20) 6.5mm × 6.4mm
DB (SSOP, 20) 7.2mm × 7.8mm
DW (SOIC, 20) 12.8mm × 10.3mm
For more information, see Section 8.
The package size (length × width) is a nominal value and includes pins, where applicable.
SN74CB3Q3244 Logic Diagram (Positive Logic) Logic Diagram (Positive Logic)
SN74CB3Q3244 Simplified Schematic, Each FET Switch
                        (SW) Simplified Schematic, Each FET Switch (SW)