SCLS761A February   2020  – October 2026 SN74HCS21-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8.   15
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 CMOS Schmitt-trigger Inputs
      3. 7.3.3 Clamp Diode Structure
      4. 7.3.4 Positive Clamp Diodes
    4. 7.4 Device Functional Modes
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

6 Parameter Measurement Information

  • Phase relationships between waveforms are chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, ZO = 50Ω, tt < 2.5ns.
  • The outputs are measured one at a time, with one input transition per measurement.
SN74HCS21-Q1 Load Circuit
A. CL= 50pF and includes probe and jig capacitance.
Figure 6-1 Load Circuit
SN74HCS21-Q1 Voltage Waveforms Propagation Delays
A. The maximum between tPLH and TPHL is used for tpd.
Figure 6-3 Voltage Waveforms Propagation Delays
SN74HCS21-Q1 Voltage Waveforms Transition TimesFigure 6-2 Voltage Waveforms Transition Times