SCLS796C January   2020  – October 2026 SN74HCS04

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Logic Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 CMOS Schmitt-Trigger Inputs
      3. 7.3.3 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Revision History

Changes from January 28, 2021 to September 29, 2026 (from Revision B (January 2021) to Revision C (October 2026))

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Changed VT+ limits at 2V VCC from 0.7V (min), 1.5V (max) to 1.13V (min), 1.37V (max) Go
  • Added VT+ typical values at 2V VCC Go
  • Changed VT+ limits at 4.5V VCC from 1.7V (min), 3.15V (max) to 2.31V (min), 2.66V (max) Go
  • Added VT+ typical values at 4.5V VCC Go
  • Changed VT+ limits at 6V VCC from 2.1V (min), 4.2V (max) to 2.99V (min), 3.44V (max) Go
  • Added VT+ typical values at 6V VCC Go
  • Changed VT- limits at 2V VCC from 0.3V (min), 1.0V (max) to 0.55V (min), 0.71V (max)Go
  • Added VT- typical values at 2V VCC Go
  • Changed VT- limits at 4.5V VCC from 0.9V (min), 2.2V (max) to 1.21V (min), 1.50V (max) Go
  • Added VT- typical values at 4.5V VCC Go
  • Changed VT- limits at 6V VCC from 1.2V (min), 3.0V (max) to 1.56V (min), 1.99V (max)Go
  • Added VT- typical values at 6V VCC Go
  • Changed ΔVT limits at 2V VCC from 0.2V (min), 1.0V (max) to 0.54V (min), 0.71V (max)Go
  • Added ΔVT typical values at 2V VCC Go
  • Changed ΔVT limits at 4.5V VCC from 0.4V (min), 1.4V (max) to 0.94V (min), 1.27V (max)Go
  • Added ΔVT typical values at 4.5V VCC Go
  • Changed ΔVT limits at 6V VCC from 0.6V (min), 1.6V (max) to 1.20V (min), 1.57V (max)Go
  • Added ΔVT typical values at 6V VCC Go

Changes from Revision A (June 2020) to Revision B (January 2021)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Added BQA package information to Device InformationGo
  • Added BQA package information to Pin Configurations and FunctionsGo
  • Added BQA package information to Thermal Information tableGo