SCLSA22A October   2024  – August 2025 SN74LV4040B-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements, VCC = 2.5V ± 0.2V
    7. 5.7  Timing Requirements, VCC = 3.3V ± 0.3V
    8. 5.8  Timing Requirements, VCC = 5V ± 0.5V
    9. 5.9  Switching Characteristics, VCC = 2.5V ± 0.2V
    10. 5.10 Switching Characteristics, VCC = 3.3V ± 0.3V
    11. 5.11 Switching Characteristics, VCC = 5V ± 0.5V
    12. 5.12 Noise Characteristics
    13. 5.13 Operating Characteristics
  7. 6 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced CMOS Push-Pull Outputs
      2. 8.3.2 Standard CMOS Inputs
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Considerations
        2. 9.2.1.2 Input Considerations
        3. 9.2.1.3 Output Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5.9 Switching Characteristics, VCC = 2.5V ± 0.2V

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE MIN TYP MAX UNIT
fmax CL = 50pF 35 95 MHz
tPLH CLK QA CL = 50pF 1 10.5 28 ns
tPHL 1 10.5 28
tPHL CLR Any Q CL = 50pF 1 11.7 28 ns
∆tpd Qn Qn+1 CL = 50pF 1.7 11.1