SCPS287F November   2023  – April 2026 TPLD1201

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I/O Pins
        1. 7.3.1.1 Input Modes
        2. 7.3.1.2 Output Modes
        3. 7.3.1.3 Pull-Up or Pull-Down Resistors
      2. 7.3.2 Connection Mux
      3. 7.3.3 Configurable Use Logic Blocks
        1. 7.3.3.1 2-Bit LUT Macro-Cell
        2. 7.3.3.2 3-Bit LUT Macro-Cell
        3. 7.3.3.3 2-Bit LUT or D Flip-Flop or Latch Macro-Cell
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop or Latch with Set or Reset Macro-Cell
        5. 7.3.3.5 3-Bit LUT or Pipe Delay Macro-cell
        6. 7.3.3.6 4-Bit LUT or 8-Bit Counter or Delay Macro-Cell
      4. 7.3.4 8-Bit Counters and Delay Generators (CNT/DLY)
        1. 7.3.4.1 Delay Mode
        2. 7.3.4.2 Edge Detector Mode
        3. 7.3.4.3 Reset Counter Mode
      5. 7.3.5 Programmable Deglitch Filter or Edge Detector Macro-Cell
      6. 7.3.6 Selectable Frequency Oscillator
      7. 7.3.7 Analog Comparators (ACMP)
      8. 7.3.8 Voltage Reference (VREF)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.1.3 Pull-Up or Pull-Down Resistors

All I/O pins have the option of user-selectable resistors that can be connected to the pin structure. The selectable values on these resistors are 10kΩ, 100kΩ and 1MΩ. The internal resistors can be configured as either pull-up or pull-down. When designing in InterConnect Studio, any pin left unused in a design are configured with a 1MΩ pull-down by default. Furthermore, following a power-on event, all ports are in a Hi-Z state until the power-on reset sequence has completed.

Table 7-1 Pin Configuration Options
GPIO IO Selection OE IO Options Resistor Resistor Value
IN0 PIN not used — — Pull-Down 1MΩ
Digital input 0 Digital in without Schmitt trigger
Digital in with Schmitt trigger
Low-voltage digital input		 Floating —
Pull-Down 10kΩ
100kΩ
1MΩ
IO1, IO2 Pin not used — — Pull Down 1MΩ
Digital input 0 Digital in without Schmitt trigger
Digital in with Schmitt trigger
Low-voltage digital input		 Floating —
Pull-Up 10kΩ
100kΩ
1MΩ
Pull-Down 10kΩ
100kΩ
1MΩ
Digital output 1 Push-pull (1X, 2X) Floating —
Open-drain NMOS (1X, 2X)
Open-drain PMOS (1X, 2X)		 Floating —
Pull-Up 10kΩ
100kΩ
1MΩ
Pull-Down 10kΩ
100kΩ
1MΩ
Digital input/output 0 Analog input — —
1 Open-drain NMOS (1X, 2X) Floating —
Pull-Up 10kΩ
100kΩ
1MΩ
Pull-Down 10kΩ
100kΩ
1MΩ
Analog input/output — Analog input/output Floating —
Pull-Up 10kΩ
100kΩ
1MΩ
Pull-Down 10kΩ
100kΩ
1MΩ
IO4, IO7 Pin not used — — Pull-Down 1MΩ
Digital input

0

 Digital in without Schmitt trigger
Digital in with Schmitt trigger
Low-voltage digital input		 Floating —
Pull-Up 10kΩ
100kΩ
1MΩ
Pull-Down 10kΩ
100kΩ
1MΩ
Digital output

1/0

 Push-pull (1X, 2X) Floating —
Open-drain NMOS (1X, 2X)
3-state output (1X, 2X)		 Floating —
Pull-Up 10kΩ
100kΩ
1MΩ
Pull-Down 10kΩ
100kΩ
1MΩ
Digital input/output 0 Digital in without Schmitt trigger
Digital in with Schmitt trigger
Low-voltage digital input
Analog input (IO4 only)		 Floating —
Pull-Up 10kΩ
100kΩ
1MΩ
Pull-Down 10kΩ
100kΩ
1MΩ
1 Push-pull (1X, 2X)
Open-drain NMOS (1X, 2X)		 Shared with above
Analog input/output — Analog input/output Floating —
Pull-Up 10kΩ
100kΩ
1MΩ
Pull-Down 10kΩ
100kΩ
1MΩ
IO5, IO6, IO9 Pin not used — — Pull Down 1MΩ
Digital input 0 Digital in without Schmitt trigger
Digital in with Schmitt trigger
Low-voltage digital input		 Floating —
Pull-Up 10kΩ
100kΩ
1MΩ
Pull-Down 10kΩ
100kΩ
1MΩ
Digital output 1 Push-pull (1X, 2X) Floating —
Open-drain NMOS (1X, 2X)
Open-drain PMOS (1X, 2X)		 Floating —
Pull-Up 10kΩ
100kΩ
1MΩ
Pull-Down 10kΩ
100kΩ
1MΩ
Note: GPI/IN0 also has the option to reset the device while powered on. Unlike POR, External Reset only resets the internal logic and routing, inputs, and outputs. The NVM retains its previous state. If GPI Reset is enabled, ensure that the input mode is set to Digital Input without Schmitt trigger.
Users select whether the External Reset is Disabled, Level sensitive, or Edge triggered.
When Level sensitive is selected, if the input is High, then the device is in reset mode where all internal devices are reset. When this pin goes Low, then the device begins the reset power on sequence.
When Edge triggered is selected, the edge detector can be configured to Rising edge or Falling edge, and an edge on GPI/IN0 resets the device and begins the reset power on sequence.