The IEC 61000-4-5 standard specifies the details for the SI test including test criteria and setup requirements. The setup includes the test equipment and procedures for performing surge testing at a specific source impedance and coupling mode (line-to-line or line-to-ground). The IEC61000-4-5 test determines the EUT immunity to external high energy surges on both power and data lines. These energy surges can be caused by power system switching, load changes and short circuit faults, or direct or indirect lighting strikes. The IEC 61000-4-5 specifies two types of combination wave generators (CWGs). The 10µs / 700µs CWG is specifically used to test the ports of symmetrical telecommunication lines. The 1.2µs / 50µs CWG is used for all other cases. The surge for all other cases combines a 1.2µs / 50µs (1.2µs rising time with 50µs pulse width) open-circuit voltage waveform and 8µs / 20µs (8µs rising time with 20µs pulse width) short-circuit current waveform. The EUT is subject to two positive and two negative surges at each rating. The surge is repeated at least once per minute. A coupling/decoupling network (CDN) is required by the surge test. The IEC 61000-4-5 defines the impedance and capacitance used in the coupling network in different cases. The EUT is tested with the surge through a CDN with a 0.5µF capacitor and a twisted cable.

Figure 3-11 Diagram of Laboratory Setup for SI Test

Table 3-9 specifies the IEC 61000-4-5 test levels:

The surge generator uses a 2Ω output impedance to model the source impedance of a low voltage power supply and the inherent source impedance of the waveform generator. An additional series resistance may be needed between the EUT and the surge generator based on the power and data line test requirements. The surge current is determined by the surge voltage level and the total impedance (Req), where Req is the combination of the surge generator output impedance and the additional series resistance. The selection of the impedance depends on the equipment type and test requirements.

Table 3-10 shows the surge current levels for different surge voltages and impedances:

Figure 3-12 shows the actual setup for the SI test on the ADS125H18 EMC test board.

Figure 3-12 Laboratory Setup for SI Test

Figure 3-13 shows the ADS125H18 EMC test board output data during the SI test (±1kV, line-to-line, 42Ω) when the ADC measures the voltage input (left) and the current input (right). The plots show that the surge signals affected the ADS125H18 output resulting in large spikes and a temporary performance loss during the test. However, the device recovered without any intervention after the disturbance stopped. Therefore, the ADS125H18 EMC test board passed the SI test with criteria B.

Figure 3-13 Voltage (Left) and Current (Right) Measurements Captured During SI Test

Table 3-11 shows the results of the SI test. The test result is the same for both the voltage and current channels on the EMC test board.