System peripherals such as GPIOs, CPU Timers, Interrupts, and Crossbars (X-BARs) play a crucial role in system-level integration and observability. These peripherals act as the backbone for interconnecting modules, enabling firmware diagnostics, and managing real-time execution control.

In this application, they are used for various key purposes — to route internal events to external pins for debugging and monitoring, to connect one peripheral’s output to another’s input for functional coordination, to generate and link interrupts with their corresponding ISR routines in firmware, and to profile code execution time or measure performance of specific code sections. Together, these system peripherals provide the essential glue logic that binds the analog, control, and digital subsystems into a unified and responsive embedded control platform.

CPU Timer Initialization:

In this application, two CPU timers are utilized for distinct purposes: Timer1 for periodic interrupt generation and ProfilingTimer for execution-time measurement.

Timer1 is configured using the CPUTIMER1 instance with a timer period value of 3030. The corresponding interrupt is enabled and linked to the INT_Timer1_ISR service routine. Based on the configured parameters, the timer overflow occurs at a frequency of 50 kHz, triggering the ISR at this rate to perform scheduled control or monitoring tasks.

The ProfilingTimer, on the other hand, is configured using the CPUTIMER2 instance. It operates with the SYSCLK as its clock source and a prescaler value of 1, providing the finest timing resolution. The timer period is set to its maximum value (65535), and the interrupt is disabled. This timer is exclusively used for profiling and benchmarking within the firmware, allowing precise measurement of code execution time for various user-defined sections.

Figure 3-18 CPU Timer Configuration.

Interrupt Initialization:

These interrupts are not configured separately under the interrupt configuration section. Instead, they are automatically configured when the corresponding interrupt is enabled within the Timer or PWM modules. This automation ensures proper interrupt mapping and linkage to their respective Interrupt Service Routines (ISRs) without requiring additional manual setup.

Ensure that the linked ISRs are correctly displayed and verified in the Interrupt Configuration view, as illustrated in the figure.

Figure 3-19 Interrupt Configuration.

XBAR Initialization:

The Crossbar modules (X-BARs) serve as internal interconnects that link various on-chip peripherals and also facilitate signal routing to the external world.

• EPWMXBAR and CLBXBAR provide input connections to the EPWM and CLB peripherals respectively, enabling flexible event routing within the device.

• OUTPUTXBAR and CLBOUTPUTXBAR are used to route internal signals to external GPIO pins, allowing visibility for debugging and signal monitoring.

• INPUTXBAR enables routing of external GPIO inputs to internal peripherals for event triggering or control logic.

Figure 3-20 XBAR Configuration.

In this application, the XBARs are configured as illustrated in the figure, enabling signal-level coordination between EPWM, CLB, and external interfaces.

GPIO Initilaization:

As shown in the figure, one of the GPIOs is configured as an output signal from the application, which can be used as an input to the Synchronous Rectifier (SR) controller. This signal facilitates coordination between the main converter and the SR stage for efficient and synchronized operation.

Figure 3-21 GPIO Configuration.