SDAA230 January 2026 DS90UB971-Q1
The two previously presented options are not robust against conditions when the PoC voltage is lower than the threshold voltage for an extended time period during normal mode. This leads to a power down of the serializer through the PDB pin as shown in the diagram in Figure 3-4.
A third option to implement the voltage detection circuit on the serializer side is by using a programmable logic device which allows designers to choose a custom configuration to avoid unwanted activation of the sleep mode condition during normal mode. Table 3-3 shows the function table for an example configuration of the voltage detection function with a programmable logic device.
| Input | Output | |
|---|---|---|
| IN_1 | IN_2 | PDB |
| Low | VIN_2 < VTHR | Low |
| High | VIN_2 < VTHR | High |
| Low | VIN_2 > VTHR | High |
| High | VIN_2 > VTHR | High |
In this example, the IN_1 pin acts as an enable input for sleep mode control. If the input on the IN_1 pin is logic low and the voltage on the IN_2 pin is below the configured threshold, the output pin which is connected to the PDB pin of the serializer is set to low and powers down the serializer. This avoids unintended sleep mode activation when the PoC voltage falls below the configured voltage threshold in normal mode operation. Figure 3-5 shows the implementation with the programmable logic device for the above example configuration. The IN_1 input is connected to a GPIO of the PMIC, which is controlled over I2C from a remote host ECU. Depending on the system architecture this can be also a GPIO pin from the image sensor.
TI offers a variety of programmable logic devices suitable for the voltage detection function like TPLD1201-Q1 with integrated comparators, LUTs, counters and oscillators.