The selection of an active clamp capacitor requires careful consideration of multiple design trade-offs involving voltage ripple, transient response characteristics, and overall efficiency. Key design parameters include the capacitance value (

) and voltage rating. The designer must evaluate the resonant frequency relative to the switching frequency, ensuring the capacitance is sufficiently large to minimize voltage ripple while remaining small enough to facilitate rapid transient response. Additionally, low equivalent series resistance (ESR) capacitor types, such as ceramic capacitors, should be selected to effectively handle resonant currents without generating excessive heat dissipation or voltage overshoot during switching transitions.

1. Determine Operating Voltages:

   When using ACL, the Vds of secondary SR FETs is clamped to

   Equation 8. ${\mathrm{V}}_{\mathrm{d}\mathrm{s}\_\mathrm{s}\mathrm{r}}=\mathrm{K}\times {\mathrm{V}\mathrm{i}\mathrm{n}}_{\mathrm{m}\mathrm{a}\mathrm{x}}\times \mathrm{N}\mathrm{s}/\mathrm{N}\mathrm{p}$

   in which K is less than 1.5

   Given that the clamping capacitors are connected in parallel with the SR FETs, the voltage across the clamping capacitors is equivalent to the drain-to-source voltage (Vds) of the SR FETs. It is important to note that the clamping capacitors are also subjected to a DC bias voltage equal to:

   Equation 9. ${\mathrm{V}}_{\mathrm{d}\mathrm{c}\_\mathrm{b}\mathrm{i}\mathrm{a}\mathrm{s}}=2\times \mathrm{D}\times {\mathrm{V}\mathrm{i}\mathrm{n}}_{\mathrm{m}\mathrm{a}\mathrm{x}}\times \mathrm{N}\mathrm{s}/\mathrm{N}\mathrm{p}$

   in which D is effective duty on transformer primary winding,

   Equation 10. $0\le D<0.5$
2. Select Resonant Frequency (
   Equation 11. $f_r$
   ):

   Set

   Equation 12. $f_r$
   significantly lower than resonant frequency without ACL
   Equation 13. $f_R$
   (for example,
   Equation 14. $f_r\approx 0.1\times f_R$
   or less).
   Equation 15. $f_R=\frac{1}{2\times \mathrm{\pi }\times \sqrt{{\left({\displaystyle \frac{\mathrm{Ns}}{\mathrm{Np}}}\right)}^2\times {\mathrm{L}}_{\mathrm{r}}\times 2\times {\mathrm{C}}_{\mathrm{oss}}}}$
   Equation 16. $f_r=\frac{1}{2\times \mathrm{\pi }\times \sqrt{{\left({\displaystyle \frac{\mathrm{Ns}}{\mathrm{Np}}}\right)}^2\times {\mathrm{L}}_{\mathrm{r}}\times ({\mathrm{C}}_{\mathrm{clamp}}+2\times {\mathrm{C}}_{\mathrm{oss}})}}$
3. Calculate
   Equation 17. $C_{clamp}$
   :

   Using the PSFB topology as an example, $C_{clamp}=1/({(Ns/Np)}^2{\times L}_r\times (2\pi f_r{)}^2)$ , where $L_r$ represents the resonant inductor on the primary side. For other topologies without a discrete resonant inductor, Lr is equivalent to the leakage inductance of the transformer secondary winding. A larger $C_{clamp}$ results in a lower resonant frequency $f_r$ , which corresponds to reduced voltage ripple across the capacitors. This reduction in capacitor voltage ripple decreases the Vds stress on the SR FETs; however, this also degrades the transient response performance of the converter.

4. Check
   Equation 18. $I_{clamp}$
   :

   Suppose the designed K is 1.1, voltage ripples on capacitors is $0.1\times Vin\times Ns/Np$ . Then $I_{clamp}$ can be derived from

   Equation 19. ${\mathrm{I}}_{\mathrm{c}\mathrm{l}\mathrm{a}\mathrm{m}\mathrm{p}}={\mathrm{C}}_{\mathrm{c}\mathrm{l}\mathrm{a}\mathrm{m}\mathrm{p}}\times (0.1\times \mathrm{V}\mathrm{i}\mathrm{n}\times \mathrm{N}\mathrm{s}/\mathrm{N}\mathrm{p})\times T_{delay}\times \mathrm{f}\mathrm{r}$

   Based on $I_{clamp}$ and temperature rise data of capacitors, you can decide the number of capacitors. Notice, $I_{clamp}$ is the rms current in clamping time . Find more details about $T_{delay}$ in Section 2.3.1.

5. Select Capacitor Type:

Use low-ESR ceramic capacitors (such as X7R or C0G etc.) for high-frequency AC performance.