SDAA294A March   2026  – May 2026 LMK6B

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2The LMK6Bx BAW Oscillator
  6. 3TI Clock Buffers
    1. 3.1 The LMKDB1x LP-HCSL Buffer Family
    2. 3.2 The LMK1Dx LVDS Buffer Family
  7. 4Clocking LMKDB1x with LMK6Bx
    1. 4.1 Clocking LMKDB1x Buffer with a LP-HCSL Oscillator
  8. 5Clocking the LMK1Dx with the LMK6Bx
    1. 5.1 Clocking LMK1Dx Buffer with a LP-HCSL Oscillator
  9. 6Summary
  10. 7References
  11. 8Revision History

3.2 The LMK1Dx LVDS Buffer Family

The high-performance LMK1Dx LVDS buffer family can be used as a MUX and has either one set of 2 inputs to four, eight, 12, or 16 outputs or two sets of one input to two, four, six, or eight outputs. This device can support 1.8V, 2.5V, and 3.3V. Figure 3-3 and Figure 3-4 illustrate these different input to output terminations. The LMK1Dx inputs can be interfaced with LVDS, LVPECL, HCSL or LVCMOS drivers. At 156.25MHz, the typical additive jitter is 50fs and at 312.5MHz the typical additive jitter is 31fs. The LMK1Dx has a high-swing LVDS option (HS-LVDS) with 500mV VOD typical to provide a higher slew rate at the outputs.

LMK1D12x Simplified Block DiagramFigure 3-3 LMK1D12x Simplified Block Diagram
LMK1D21x Simplified Block DiagramFigure 3-4 LMK1D21x Simplified Block Diagram

For more information about the LMK1D12x, see the LMK1D12x datasheet and for more information about the LMK1D21x, refer to LMK1D21x datasheet.