SDAA408 July 2026 TUSB7320 , TUSB7340

4 Memory-Mapped I/O (MMIO) Register Configuration

To force the TUSB7320/TUSB7340 downstream ports into USB 2.0 Compliance Mode without relying on high-level kernel drivers, software can directly manipulate the xHCI Operational Registers mapped into system memory. This section utilizes the ⁠busybox devmem⁠ utility to perform low-level read/write operations directly to the physical memory addresses.

Execute ⁠lspci⁠ to Locate the Host Controller on the PCI Bus

Before interacting with the hardware memory space, scan the PCI bus topology to identify the specific Bus, Device, and Function (BDF) address assigned to the Texas Instruments controller by the system architecture.

Execute the basic ⁠lspci⁠ utility to list all peripheral components connected to the PCI lanes:

lspci

Once the target entry is located (e.g., ⁠01:00.0⁠), re-run the command with the specific BDF slot and verbose hexadecimal dumping parameters to extract the 64-bit Base Address Register (BAR) mapping:

sudo lspci -s <BUS:DEV.FUN> -vxx

Identify the 64-bit memory base address corresponding to the xHCI Operational Registers from the output fields. Note that the controller allocates multiple memory regions; select the address entry specified with [size=64K] (e.g., Memory at f79f0000). This address serves as the foundational Base Address for all subsequent register offset calculations.

Halt the xHCI Controller

Before forcing individual ports into electrical compliance test modes, the xHCI controller must be halted to prevent operational software loops or interrupt routines from overriding the register states.

Modify the USB Command (USBCMD) register (Offset ⁠0x20⁠ from the base address) by clearing the Run/Stop bit to ⁠0⁠. Execute the following 8-bit ⁠devmem⁠ command:

sudo busybox devmem <Base_Address + 0x20> 8 4

Power Off the Target Downstream Port

To properly cycle the port logic and prepare the transceiver for compliance mode transition, the power to the specific downstream port must be negated.

Locate the Port Status and Control (PORTSC) register offset for the target port. Write to clear the port power bits utilizing a 32-bit width command:

sudo busybox devmem <Base_Address + Port_Offset> 32 0x0A000080

Transmit the USB 2.0 Test Pattern

Once the port is successfully sequenced, select the desired compliance test mode by writing to the ⁠Port Test Control⁠ field within the associated test register space (Offset ⁠+ 0x4⁠ from the base Port Offset).

To transmit a continuous USB 2.0 High-Speed Test Packet pattern (required for electrical eye-diagram analysis), execute the following 32-bit command:

sudo busybox devmem <Base_Address + Port_Offset + 0x4> 32 0x40000000

Upon successful execution, the physical layer (PHY) of the targeted port will immediately initiate continuous pattern generation.

Physical Ports Address

To test alternative physical ports, shift the target memory addresses based on the following table:

Table 4-1 TUSB7320/TUSB7340 Downstream Port Register Offsets

Port	Control Address	Test Command Address
1	0x0420	0x0424
2	0x0430	0x0434
3	0x0440 ⁽¹⁾	0x0444 ⁽¹⁾
4	0x0450 ⁽¹⁾	0x0454 ⁽¹⁾

TUSB7340 only

Execution Example

This section provides an actual implementation on Port1. The walkthrough is captured from a live test environment utilizing a standard Ubuntu platform.

Running the ⁠lspci⁠ discovery command yields:
Figure 4-1 Discovery Command for PCI Address
Figure 4-2 Command for Base Address
Key Terminal Output Extracted:
- PCI Address (BDF): ⁠01:00.0⁠
- 64-bit Base Address (BAR): ⁠0xf79f0000⁠ (from ⁠Memory at f79f0000⁠)
Full Test Packet Trigger Command Sequence. Using the extracted Base Address (⁠0xf79f0000⁠), the exact register execution log to trigger Port 1 (Control Address ⁠0x420, Test Command address 0x424⁠) into Test Packet Mode is detailed below:
Figure 4-3 Command for Triggering Test Packet