SDAA428 June   2026 TMS320F28P650DK

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Dual Core Architecture in C28x family
    1. 2.1 Homogenous Architecture (C28x + C28x)
    2. 2.2 Heterogenous Architecture (C28x + C28X + ARM Cortex M4)
      1. 2.2.1 TMS320F2838x (F28388D, F28386D, etc.)
  6. 3General Flow for a dual-core application
  7. 4Boot Sequence
  8. 5Running a simple dual core example
  9. 6Key Pitfalls
  10. 7One-click solution for dual core flashing
  11. 8Inter Processor Communication
  12. 9Helpful Links

1 Introduction

When it comes to real-time control applications, there is always a fundamental concern. Deterministic hard-real-time control loops (typically running at frequencies in the order of 100 kHz) cannot share compute time with slower supervisory tasks such as communications, protection logic, telemetry, fault management etc. A second CPU alleviates this concern by dividing the overall workload and allowing for a single CPU's dedicated bandwidth to real-time-control related tasks. This application note explores how to effectively debug applications that might show unexpected behaviors in a dual core environment. It talks about how boot up sequence and memory or peripherals ownership conflicts can lead to the erratic performance of a dual core application.