SDAA429 June   2026 MSPM0G5187

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2MSPM0G5187 with TinyEngine NPU
  6. 3Edge AI Toolchains
    1. 3.1 TI Edge AI Studio
    2. 3.2 TI Tiny ML Tensorlab
    3. 3.3 TI Neural Network Compiler
  7. 4Edge AI Application: Digit Recognition
    1. 4.1 LeNet-5 Variant CNN Model
    2. 4.2 NPU/CPU Performance Comparison
  8. 5Edge AI Application: Waveform Classifier
    1. 5.1 Feature Extraction
    2. 5.2 Time-Series Classification Model
    3. 5.3 Model Memory Considerations
    4. 5.4 NPU/CPU Performance Comparison
  9. 6Summary
  10. 7References

3.3 TI Neural Network Compiler

The TI Neural Network Compiler (NNC) is TI's embedded AI compilation toolchain for MCU devices, built on the TVM compiler framework. TI NNC enables flexible deployment of the AI model to either the hardware NPU accelerator or the host CPU through a simple compilation configuration, with no changes required to the application code or model side. The inference is always invoked through the unified interface, enabling developers to integrate AI inference into embedded applications without requiring deep knowledge of the underlying hardware architecture.

Table 3-2 NPU/CPU Deployment Configuration Comparison
Target Deployment Configuration Symbol Initialization Requirement Invoke Inference
Host CPU TVMGEN_DEFAULT_TI_NPU_SOFT Yes, initialize NPU before Inference tvmgen_default_run()
Hardware NPU TVMGEN_DEFAULT_TI_NPU No

For more information, see TI Neural Network Compiler for MCUs User’s Guide.