SFFS033 September 2021 THS4509-Q1
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a Failure Mode Analysis (FMA) for the pins of the THS4509-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to Ground (see Table 4-2)
- Pin open-circuited (see Table 4-3)
- Pin short-circuited to an adjacent pin (see Table 4-4)
- Pin short-circuited to supply (see Table 4-5)
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Table 4-1 TI Classification of Failure Effects
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality |
| B | No device damage, but loss of functionality |
| C | No device damage, but performance degradation |
| D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the THS4509-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the THS4509-Q1 data sheet.
Figure 4-1 Pin DiagramFollowing are the assumptions of use and the device configuration assumed for the pin FMA in this section:
- Assumption – the device is running in the typical application, please refer to the Simplified Schematic on the first page of the THS4509-Q1 Wideband Low-Noise Low-Distortion Fully Differential Amplifier data sheet.
- Total supply voltage of 5 V with V+ connected to 2.5 V and V- connected to -2.5 V.
- Input and output pins biased to GND reference point.
Table 4-2 Pin FMA for Device Pins
Short-Circuited to Ground
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| NC | 1 | Normal operation. Pin has no internal connection. | D |
| VIN- | 2 | Input at mid-supply (GND) is valid input; however, the application's desired result is unlikely. | C |
| VOUT+ | 3 | May cause device to overheat. | B |
| CM | 4 and 9 | Normal operation, unless single supply voltage was intended. | D |
| VS+ | 5, 6, 7, and 8 | Diodes from input to VS+ may turn on due to input signal and cause electrical overstress (EOS). | A |
| VOUT- | 10 | May cause device to overheat. | B |
| VIN+ | 11 | Input at mid-supply (GND) is valid input; however, the application's desired result is unlikely. | C |
| PD | 12 | Valid Input. Device will function normally with dual supplies and in low-power mode if single supply configuration is used. | D |
| VS- | 13, 14, 15, and 16 | Diodes from input to VS- may turn on due to input signal and cause electrical overstress (EOS). Normal Operation if single supply configuration is used. | A |
Table 4-3 Pin FMA for Device Pins
Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| NC | 1 | Normal operation. Pin has no internal connection. | D |
| VIN- | 2 | Floating input, circuit will likely not function as expected. | C |
| VOUT+ | 3 | Output can be left open. There is no effect on the IC, but the output will not be measured. | C |
| CM | 4 and 9 | Normal operation. Output common-mode will be set to mid-supply. | D |
| VS+ | 5, 6, 7, and 8 | Highest voltage output pin will try to power the device's VS+ pin. | B |
| VOUT- | 10 | Output can be left open. There is no effect on the IC, but the output will not be measured. | C |
| VIN+ | 11 | Floating input, circuit will likely not function as expected. | C |
| PD | 12 | Power down pin can be left open for normal operation. | D |
| VS- | 13, 14, 15, and 16 | Lowest voltage output pin will try to power the device's VS-pin. | B |
Table 4-4 Pin FMA for Device Pins
Short-Circuited to Adjacent Pin
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|---|
| 1 | NC | VIN- | Normal operation. NC pin has no internal connection. | D |
| 2 | VIN- | VOUT+ | Tying input pin to an output pin is valid, however, the application's desired result is unlikely. | C |
| 3 | VOUT+ | CM | Tying output pin to CM pin is valid; however, the application's desired result is unlikely. | C |
| 4 | CM | VS+ | Tying output pin to VS+ pin is valid; however, the application's desired result is unlikely. | C |
| 5, 6, and 7 | VS+ | VS+ | Normal operation. Pins are connected internally. | D |
| 8 | VS+ | CM | Tying output pin to VS+ pin is valid; however, the application's desired result is unlikely. | C |
| 9 | CM | VOUT- | Tying Output pin to CM pin is valid; however, the application's desired result is unlikely. | C |
| 10 | VOUT- | VIN+ | Tying input pin to an output pin is valid; however, the application's desired result is unlikely. | C |
| 11 | VIN+ | PD | Tying an input pin to the power-down pin is valid; however, the application's desired result is unlikely. | C |
| 12 | PD | VS- | Device will operate in low-power mode. | C |
| 13, 14, and 15 | VS- | VS- | Normal operation. Pins are connected internally. | D |
| 16 | VS- | NC | Normal operation. NC pin has no internal connection. | D |
Table 4-5 Pin FMA for Device Pins
Short-Circuited to VS+
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| NC | 1 | Normal operation. NC pin has no internal connection. | D |
| VIN- | 2 | Input at VS+ is valid input; however, the application's desired result is unlikely. | C |
| VOUT+ | 3 | May cause device to overheat. | B |
| CM | 4 and 9 | CM pin at VS+ is valid input; however, the application's desired result is unlikely. | C |
| VS+ | 5, 6, 7, and 8 | Normal operation. | D |
| VOUT- | 10 | May cause device to overheat. | B |
| VIN+ | 11 | Input at VS+ is valid input; however, the application's desired result is unlikely. | C |
| PD | 12 | Normal operation. | D |
| VS- | 13, 14, 15, and 16 | Diodes from input to V- may turn on due to input signal and cause electrical overstress (EOS). | A |