SFFS254 September 2021 TLV3603
Figure 4-1 shows the TLV3603 pin diagram for the DCK package. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the TLV3603 data sheet.
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
OUT | 1 | Thermal stress due to high power dissipation | A |
VEE | 2 | No change if same node as GND | D |
IN+ | 3 | Output goes low, if other input is positive | B |
IN- | 4 | Output goes high, if other input is positive | B |
| LE /HYST | 5 | Output may be low or high | B |
VCC | 6 | Main supply shorted out (no power to device) | B |
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
OUT | 1 | Output can't drive application load | B |
VEE | 2 | Lowest voltage pin will drive GND pin internally (via diode) | A |
IN+ | 3 | Output may be low or high | B |
IN- | 4 | Output may be low or high | B |
| LE /HYST | 5 | Output may be low or high | C |
VCC | 6 | Main supply open (no power to device) | B |
| Pin Name | Pin No. | Shorted to | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|---|
OUT | 1 | VEE | Thermal stress due to high power dissipation | A |
VEE | 2 | IN+ | Output goes low, if other input is positive | B |
IN+ | 3 | IN- | Output may be low or high | B |
IN- | 4 | LE /HYST | Output may be low or high | C |
| LE /HYST | 5 | VCC | Output may be low or high | C |
VCC | 6 | OUT | Thermal stress due to high power dissipation | A |
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
OUT | 1 | Thermal stress due to high power dissipation | A |
VEE | 2 | Main supply shorted out (no power to device) | B |
IN+ | 3 | Output goes high, if other input is less positive | B |
IN- | 4 | Output goes low, if other input is less positive | B |
| LE /HYST | 5 | Output may be low or high | C |
VCC | 6 | No change if same node as VCC | D |