SFFS288 February   2022 TPSM63606

 

  1.   Trademarks
  2. 1Overview
  3. 2Functional Safety Failure In Time (FIT) Rates
  4. 3Failure Mode Distribution (FMD)
  5. 4Pin Failure Mode Analysis (Pin FMA)

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the TPSM63606. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

  • Pin short-circuited to Ground (see Table 4-2)
  • Pin open-circuited (see Table 4-3)
  • Pin short-circuited to an adjacent pin (see Table 4-4)
  • Pin short-circuited to supply (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality
BNo device damage, but loss of functionality
CNo device damage, but performance degradation
DNo device damage, no impact to functionality or performance

Figure 4-1 shows the TPSM63606 pin diagram. For a detailed description of the device pins, please refer to the Pin Configuration and Functions section in the TPSM63606 data sheet.

Figure 4-1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin Name Pin No. Description of Potential Failure Effect(s) Failure Effect Class
VIN1, VIN2 1, 16 VOUT = 0 V. Possible damage to customer input supply, PCB can occur unless customer provides protection, or both. Reverse current from the VOUT pin to VIN pin, due to discharge of output capacitors, can damage the regulator. B
SW 2 Shorting the SW pin to ground will result in large currents through the device and subsequent damage. No output voltage will be produced. A
CBOOT 3 Driver supply to high-side MOSFET will be lost. Output voltage will not be regulated. Possible damage to the internal regulator and CBOOT charging circuit B
RBOOT 4 Loss of output voltage A
VLDOIN 5 Normal operation, IC powers from VIN, causing decreased efficiency. C
AGND 6, 11 No effect D
VCC 7 Internal circuits will be disabled. No output voltage will be generated. Possible increase in input current B
VOUT1, VOUT2 8, 9 Loss of output voltage B
FB 10 The regulator will operate at maximum duty cycle. Output voltage will rise to nearly the input voltage level. Possible damage to customer load, output stage components can occur, or both. B
RT 12 Loss of output voltage B
PG 13 This is a valid connection for the PG output. PG functionality will be lost. Damage to external components connected to PG input can occur. D
EN/SYNC 14 This is a valid connection for the EN input. Enable functionality will be lost; the device will remain off with no output voltage generated. Damage to external components connected to EN input can occur. B
NC 15 No effect D
PGND 17, 18, 19, 20 This is the recommended connection for PGND. D
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
VIN1 1 VOUT normal. Current loop will be affected, potentially affecting noise/jitter/EMI/reliability. C
SW 2 Normal operation D
CBOOT 3 Normal operation D
RBOOT 4 Normal operation D
VLDOIN 5 Normal operation, IC powers from VIN, causing decreased efficiency. C
AGND 6, 11 Load regulation degraded C
VCC 7 Normal operation D
VOUT1 8 VOUT normal. Current loop will be affected, potentially affecting noise/jitter/EMI/reliability. C
VOUT2 9 VOUT normal. Current loop will be affected, potentially affecting noise/jitter/EMI/reliability. C
FB 10 VOUT >> than programmed output voltage. B
RT 12 Loss of output voltage B
PG 13 This is a valid connection for the PG output. PG functionality will be lost. D
EN/SYNC 14 Loss of enable functionality. Erratic operation; probable loss of regulation B
NC 15 Valid connection D
VIN2 16 VOUT normal. Current loop will be affected, potentially affecting noise/jitter/EMI/reliability. C
PGND 17, 18, 19, 20 Load regulation degraded, thermal impedance impacted. Loss of operation if all four pins are open. B
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin Name Pin No. Shorted to Description of Potential Failure Effect(s) Failure Effect Class
VIN1 1 SW Damage to low-side FET A
SW 2 CBOOT Loss of high-side gate drive supply B
CBOOT 3 RBOOT Valid connection D
RBOOT 4 VLDOIN Possible damage to internal circuits A
VLDOIN 5 AGND Valid connection. Possible decrease in efficiency when VLDOIN is intended to be tied to VOUT or external bias supply D
AGND 6 VCC Internal circuits will be disabled. No output voltage will be generated. B
VCC 7 VOUT1 VCC ESD clamp damaged if VOUT > 5 V. A
VOUT1 8 VOUT2 Valid connection D
VOUT2 9 FB VOUT = 1 V B
FB 10 AGND VOUT close to VIN B
AGND 11 RT Loss of output voltage B
RT 12 PG Possible damage to internal circuits A
PG 13 EN/SYNC Possible damage to internal PG circuit if VEN/SYNC > 16 V A
EN/SYNC 14 NC No effect C
NC 15 VIN2 No effect
VIN2 16 VIN1 Valid connection D
PGND 17, 18, 19, 20 Any Other pin is shorted to ground, see Table 4-5. –
Table 4-5 Pin FMA for Device Pins Short-Circuited to Supply (VIN1 and/or VIN2)
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
VIN1, VIN2 1, 16 No effect (normal operation) D
SW 2 Damage to low-side FET A
CBOOT 3 VOUT = 0 V. CBOOT ESD clamp will run current to destruction. A
RBOOT 4 VOUT = 0 V. RBOOT ESD clamp will run current to destruction. A
VLDOIN 5 If VIN exceeds 16 V, damage will occur. If below, normal operation A
AGND 6, 11 VOUT = 0 V. Damage to other pins referred to GND A
VCC 7 If VIN exceeds 5.5 V, damage will occur. A
VOUT1, VOUT2 8, 9 Damage to low-side FET. The output voltage will rise to nearly the level of VIN. Customer load will be damaged. Possible damage to device A
FB 10 If VIN exceeds 16 V, damage will occur. VOUT = 0 V A
RT 12 VOUT = 0 V B
PG 13 VOUT = 0 V. PGOOD ESD clamp will run current to destruction. A
EN/SYNC 14 Normal operation; enable functionality will be lost, the device will remain on. D
NC 15 No effect D
PGND 17, 18, 19, 20 VOUT = 0 V. Damage to low-side circuitry if VPGND >> VAGND B