SFFS301 May   2025 LM74720-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
  7. 5Revision History

Pin Failure Mode Analysis (Pin FMA)

This section provides a failure mode analysis (FMA) for the pins of the LM74720-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality.
BNo device damage, but loss of functionality.
CNo device damage, but performance degradation.
DNo device damage, no impact to functionality or performance.

Figure 4-1 shows the LM74720-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the LM74720-Q1 data sheet.

LM74720-Q1 WSON 12-Pin DRR Transparent Top ViewFigure 4-1 WSON 12-Pin DRR Transparent Top View

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • The device is operating under the specified ranges within the Recommended Operating Conditions section of the data sheet.
Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin NamePin No.Description of Potential Failure EffectsFailure Effect Class
DGATE1The device is damaged due to internal conduction. The external DGATE FET can also be damaged due to a violation of the maximum VGS rating.A
A2Input supply shorted to ground. Device not functional.

B

VSNS3The input supply monitoring feature is not available.B
SW4No device damage is expected if VSNS is floating. The device is damaged if VSNS is connected to A.A
OV5The overvoltage protection functionality is disabled.B
EN6The device is in shutdown mode.B
GND7No impact on device functionality.D
PD8The HGATE gate drive is off.B
LX9The externals FETs are always OFF. VBATT is short to GND; the inductor can be damaged.A
CAP10The device is damaged due to internal conduction between VS and CAP.A
VS11The device does not power up. BFET is damaged. VBATT is short to GND.A
C12BFET is damaged. VBATT is short to GND.A
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin NamePin No.Description of Potential Failure EffectsFailure Effect Class
GATE1The external FET is not controlled. The system is still protected by the body diode of the FET.B
A2The DGATE drive is off. The system is still protected by the body diode of the FET.B
VSNS3The input supply monitoring feature is not available.B
SW4The input supply monitoring feature is not available.B
OV5The overvoltage pin is internal pulldown when floating. OV functionality is DISABLED.B
EN6The device is in shutdown mode due to the internal pulldown on the EN pin.B
GND7The device does not power up.B
PD8The HFET is off since the PD gate drive is open.B
LX9The boost output does not switch. BFET is OFF. The output is at VIN-2VD.B
CAP10The device detects CAP open and shuts off.B
VS11The boost converter is OFF due to no supply. Both FETS are OFF.B
C12The part powers up but latches off after one full boost cycle. The latch is cleared by the EN pin or power cycling.B
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin NamePin No.Shorted toDescription of Potential Failure EffectsFailure Effect Class
GATE1AThe DGATE FET is always off as the external FET GATE to SOURCE is shorted.B
A2VSNSNo impact on device functionality.D
VSNS3SWThe input supply monitoring feature is always available.
There is a higher system Iq when EN = low, due to constant current drawn through the external R-ladder.
B
SW4OVThe PD turns off, provided the voltage of the SW pin is higher than the overvoltage threshold of the overvoltage comparator.B
OV5ENThe PD is on or off based on the voltage level of the EN/UVLO pin being lower or higher than the overvoltage threshold of the overvoltage comparator.B
EN6GNDThe device is always OFF. No impact on device operation.B
GND7PDThe PD is pulled low and the external FET is off.B
PD8LXN/AB
LX9CAPThe boost converter diode is bypassed. The device shuts off boost after detecting the fault.B
CAP10VSThe boost operation is in closed loop (the inductor builds up from C and discharges back to VS or C) at every switching cycle. Continuous switching of boost.B
VS11CVS follows C. No impact on device operation.D
C12N/ANo impact on device operation.D
Table 4-5 Pin FMA for Device Pins Short-Circuited to Supply
Pin NamePin No.Description of Potential Failure EffectsFailure Effect Class
GATE1The diode FET is always off since the external FET GATE to SOURCE is shorted.B
A2No impact on device operation.D
VSNS3No impact on device operation.D
SW4The input supply monitoring feature is always available.B
OV5When the input of the overvoltage comparator is higher than the overvoltage threshold, the PD is off.B
EN6The device is always on. The undervoltage functionality is not available.B
GND7The input supply is shorted to ground. The device does not power up.B
PD8The PD gate drive is off when EN = high.
The PD internal pulldown FET is damaged when EN = low.
A
LX9The device shuts off boost after detecting the fault.B
CAP10The charge pump does not power up. DGATE and HGATE drive remain off.B
VS11No impact on the operation of the device when the supply voltage is positive. The device is damaged when the supply voltage is negative. A
C12The reverse-current blocking functionality is lost when the supply is positive. The device is damaged when the supply voltage is negative.A