SFFS550 March   2024 OPA2607-Q1 , OPA607-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 DBV Package
    2. 2.2 DGK Package
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 DBV Package
    2. 4.2 DGK Package

4.2 DGK Package

Figure 4-2 shows the OPAx607-Q1 pin diagram for the DGK package. For a detailed description of the device pins, see the Pin Configuration and Functions section in the OPAx607-Q1 data sheet.

GUID-483DC28B-DD78-4509-8AE1-E0F552371A85-low.gifFigure 4-2 Pin Diagram (DGK Package)
Table 4-6 Pin FMA for Device Pins Short-Circuited to Ground
Pin NamePin No.Description of Potential Failure EffectsFailure Effect Class
OUT11Short to GND may cause device to overheat.B
IN1-2Input at VS- (GND) is valid input, however, desired application result is unlikely.C
IN1+3Input at VS- (GND) is valid input, however, desired application result is unlikely.C
VS-4Normal Operation if single supply configuration is used.D
OUT25May cause device to overheat.B
IN2+6Input at VS- (GND) is valid input, however, desired application result is unlikely.C
IN2-7Input at VS- (GND) is valid input, however, desired application result is unlikely.C
VS+8Diodes from input to VS+ may turn on due to input signal and cause electrical overstress (EOS).A
Table 4-7 Pin FMA for Device Pins Open-Circuited
Pin NamePin No.Description of Potential Failure EffectsFailure Effect Class
OUT11Output can be left open. There is no effect on the device, but the output will not be measured.C
IN1-2Floating input; circuit will likely not function as expected.C
IN1+3Floating input; circuit will likely not function as expected.C
VS-4Lowest voltage output pin will try to power the VS- pin of the device.B
OUT25Output can be left open. There is no effect on the device, but the output will not be measured.C
IN2+6Floating input; circuit will likely not function as expected.C
IN2-7Floating input; circuit will likely not function as expected.C
VS+8Highest voltage output pin will try to power the VS+ pin of the device.B
Table 4-8 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin NamePin No.Shorted toDescription of Potential Failure EffectsFailure Effect Class
OUT11IN1-Channel 1 configured in unity gain.C
IN1-2IN1+No damage to device. Application circuit will not work.C
IN1+3VS-Input at V- (GND) is valid input, however, desired application result is unlikely.C
VS-4IN2+Input at V- (GND) is valid input, however, desired application result is unlikely. Pins are not adjacent to each other.C
IN2+5IN2-No damage to device. Application circuit will not work.C
IN2-6OUT2Channel 2 configured in unity gainC
OUT27VS+Short to VS+ may cause device to overheat.B
VS+8OUT1Short to VS+ may cause device to overheat. Pins are not adjacent to each other.B
Table 4-9 Pin FMA for Device Pins Short-Circuited to supply
Pin NamePin No.Description of Potential Failure EffectsFailure Effect Class
OUT11Short to VS+ may cause device to overheat.B
IN1-2Input at VS+ (GND) is valid input, however, desired application result is unlikely.C
IN1+3Input at VS+ (GND) is valid input, however, desired application result is unlikely.C
VS-4Diodes from input to VS- may turn on due to input signal and cause electrical overstress (EOS).A
OUT25Short to VS+ may cause device to overheat.B
IN2+6Input at VS+ (GND) is valid input, however, desired application result is unlikely.C
IN2-7Input at VS+ (GND) is valid input, however, desired application result is unlikely.C
VS+8Normal operation.D