SFFS837 January 2025 TPS628522-Q1 , TPS628523-Q1

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the TPS628523HA-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Pin short-circuited to Ground (see Table 4-2)
Pin open-circuited (see Table 4-3)
Pin short-circuited to an adjacent pin (see Table 4-4)
Pin short-circuited to VIN (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects

Class	Failure Effects
A	Potential device damage that affects functionality
B	No device damage, but loss of functionality
C	No device damage, but performance degradation
D	No device damage, no impact to functionality or performance

Table 4-1 shows the TPS628523HA-Q1 pin diagram. For a detailed description of the device pins, please refer to the 'Pin Configuration and Functions' section in the TPS628523HA-Q1 data sheet.

Figure 4-1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

The device is operating in the typical application. Please refer to the 'Simplified Schematics' on the first page in the TPS628523HA-Q1 data sheet.

Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground

Pin Name	Pin No.	Description of Potential Failure Effect(s)	Failure Effect Class
PG	1	No device damage, but loss of functionality	B
VIN	2	Device does not power up	B
SW	3	Potential device damage that affects functionality	A
GND	4	No device damage, no impact to functionality	D
EN	5	Device is disbaled. No device damage, but loss of functionality	B
SS	6	Output voltage will not ramp up. No device damage, but loss of functionality	B
OUT	7	No device damage, but performance degradation	C
FB	8	Open loop operation and device performance degradationC	C

Table 4-3 Pin FMA for Device Pins Open-Circuited

Pin Name	Pin No.	Description of Potential Failure Effects	Failure Effect Class
PG	1	False PG indication	B
VIN	2	Device does not power up	B
SW	3	Device not functional; open loop operation	B
GND	4	Potential device damage	A
EN	5	Undetermined device operation; device might power up or not	B
SS	6	SS time given by internal min SS time	C
OUT	7	No device damage but performance degradation	C
FB	8	Device not functional; open loop operation	B

Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin

Pin Name	Pin No.	Shorted to	Description of Potential Failure Effect(s)	Failure Effect Class
PG	1	VIN	No device damage, but performance degradation. False PG indication	C
VIN	2	SW	Potential device damage	A
SW	3	GND	Potential device damage	A
EN	5	SS	Loss of functionality	B
SS	6	OUT	Loss of functionality	B
OUT	7	FB	No device damage, but performance degradation.	C

Table 4-5 Pin FMA for Device Pins Short-Circuited to VIN

Pin Name	Pin No.	Description of Potential Failure Effect(s)	Failure Effect Class PG
PG	1	No device damage, but loss of functionality. False PG indication	B
VIN	2	Intended functionality	D
SW	3	Potential device damage	A
GND	4	Device not functional	B
EN	5	Device always enabled. No device damage, but loss of functionality in case of EN=0	B
SS	6	SS time given by internal min SS time	C
OUT	7	No device damage, but performance degradation	C
FB	8	Device not functional; Open loop operation	B